2.7. Crossbar Switch

The next step in chipset evolution was to reduce the bottleneck at the memory I/O controllers by replacing the controllers with a crossbar switch, as illustrated in Figure 2-7.

Figure 2-7. Crossbar switch.

The crossbar switch has five ports: two to the memory subsystem, two to the processor subsystem, and one to the I/O subsystem.

Employing mainframe techniques, the crossbar switch enables each of the five main ports to transfer data at high speed to each of the other ports, allowing concurrent read/writes between processors, memory, and I/O. Although there are two physical system buses, the buses present one system image logically to the operating system.