2.6. Highly Parallel System Architecture

Peer I/O buses moved the bottleneck from the I/O subsystem back to the memory controller. Dual memory controllers were the next step in chipset evolution. This system architecture design was called the Highly Parallel System Architecture (HPSA), and is shown in Figure 2-6.

Figure 2-6. Highly Parallel System Architecture.

This architecture also featured dual peer PCI buses. HP co-developed this powerful technology with ServerWorks and was the first to bring it to market.

HPSA servers employing dual memory controllers processed memory requests in parallel, enabling memory bandwidth to achieve up to 1.6GB/s with 100MHz (2.12GB/s with 133MHz) SDRAM.

HPSA components include the following:

• Assisted Gunning Transceiver Logic plus (AGTL+) bus

• Intel Pentium II and III processors

• Dual Wide-Ultra SCSI controllers

• Dual-peer PCI buses

• Dual memory controllers

• Interleaved memory