2.2. Dual Independent Buses

To alleviate the problems caused by a single system bus, the next step was to split the bus into two independent buses. This was known as dual independent bus architecture. This architecture is shown in Figure 2-2.

Figure 2-2. Dual independent bus architecture.

HP introduced the first dual independent bus design. This design allowed the memory bus between the processor and memory to operate at a higher speed than that of the I/O expansion bus. An I/O bridge was used to synchronize data transfers between the two buses.

In this architecture, the bottleneck now shifted to the I/O bridge. All I/O devices were contending with the I/O bridge to communicate with the host bus. To solve this problem, buffers were added to the bridge. If the bridge was busy transferring data from one I/O device, it would buffer the data from other I/O devices. When the bus was free, the bridge sent the buffered data. This enabled the I/O devices to continue working and not wait for a response from the bridge.