| PCI-X is a superset of the PCI bus that provides a relaxed ordering bit, which changes the PCI-X ordering rules from PCI. PCI-X also uses different transaction types and protocols, requiring a very different bridge design than PCI; however, the bridge must be compatible with PCI protocols. PCI-X Ordering Requirements PCI-X ordering is based on the same principles as PCI; thus, the ordering rules are very similar. In fact, the only differences are due to the Relaxed Ordering supported by PCI-X. Table 20-4 on page 468 lists the PCI-X ordering rules. Note that Posted Memory Writes (PMW) and Split Request Completions (SRC) support Relaxed Ordering, yielding to possible ordering scenarios for each case in Column 1. PCI-X also supports split transactions rather than delayed transactions. The terms and acronyms below reflect the split transaction types: -
PMW stands for posted memory write. -
SRR and SRC stand for Split Read Request and Split Read Completion, respectively. -
SWR and SWC stand for Split Write Request and Split Write Completion, respectively. -
"Yes" specifies that the transaction just latched must be ordered ahead of the previously latched transaction indicated in the column heading. -
"No" specifies that the transaction just latched must never be ordered ahead of the previously latched transaction indicated in the column heading. -
"Yes/No" entries means that the transaction just latched is allowed to be ordered ahead of the previously-latched operation indicated in the column heading, but such reordering is not required. Table 20-4. PCI-X Ordering Rules | Transaction just latched | Posted Memory Write | Split Requests | Split Completions | | PMW Column 1 | SRR Column 2 | SWR Column 3 | SRC Column 4 | SWC Column 5 | | PMW (row 1) | RO=0: No RO=1: Yes/No | Yes | Yes | Yes | Yes | | SRR (row 2) | No | Yes/No | | SWR (row 3) | No | | SRC (row 4) | RO=0: No RO=1: Yes/No | Yes | Yes/No | | SWC (row 5) | Yes/No | Transaction Translation PCI-X replaces delayed transactions with split transactions, and supports a Relaxed Ordering bit and the No Snoop bit to enhance performance, causing command conversion to vary slightly from PCI. Table 20-5 on page 468 lists the command conversion from PCI-X to HT and Table 20-6 on page 469 lists the command conversion from HT-to-PCI-X. Please note that later versions of the specification were pending completion at the time of this writing and may add new information to the transaction tables. Table 20-5. PCI-X to HT Command Conversion | PCI -X Transaction Type | HyperTransport Packet Type | | Posted Memory Write | WrSized, Posted, PassPW = RO, Data Error=PERR# [1] | | Split Read Request | RdSized, PassPW = 0, RespPassPW = RO, Coherent = Snoop | | Split Write Request | WrSized, Nonposted, PassPW = 0 [2] | | Split Read Completion | RdResponse, PassPW = RO, Data Error=PERR# [1] | | Split Write Completion | TgtDone, PassPW = 1 [4] , Data Error=PERR# [3] | [1] DataError is set if the bridge detected a parity error or (in mode 2) an unrecoverable ECC error. [2] Split Write requests with data errors are discarded if the Parity Error Response Enable is set. [4] To ensure correct ordering of some message sequences (e.g., Interrupt and STPCLK virutal signaling) the PassPW bit must be cleared in the TgtDone . [3] DataError is set if a data parity error is detected during a Split Write Completion, and the write is discarded (only if Parity Error Response Enable is set). Table 20-6. HT-to-PCI-X Command Conversion | HyperTransport Packet Type | PCI -X Transaction Type | | WrSized to Memory Space [2] | Posted Memory Write, RO=PassPW [1] | | WrSized to Configuration or I/O Space | Split Write Request [2] | | RdSized | Split Read Request [3] , RO = RespPassPW [1] | | RdResponse | Split Read Completion, RO = PassPW | | TgtDone | Split Write Completion | | 4. The No Snoop bit in PCI -X requests from HT bridges is always 0. | [2] All memory writes on PCI are posted regardless of whether they are posted on HT or not. [1] RO is the Relaxed Ordering bit in PCI -X. If RO=0, PassPW and RespPassPW must be 0. RO must never be set in requests, regardless of the value of PassPW or RespPassPW [3] Split Requests are never posted operations and will always result in a Read Response or Target Done.  |
