10.5 Embedded mixed-signal test cores

10.5 Embedded mixed-signal test cores

In light of the discussion in Section 10.4, we note that many of the challenges facing the continued usefulness of automatic test equipment are related to limited integration levels. Specifically, it was shown that limited parallelism is expected to exist on a test platform unless major integration efforts are undertaken by the ATE vendor. Similarly, it was mentioned that traditional test setups place a DUT in an environment that is very different from its mission environment. For high-frequency parts that are not expected to drive long interconnects in the field, extracting realistic device performance data in such an environment becomes extremely challenging. In order to deal with some of these challenges, design-for-test approaches that enhance the testability of mixed-signal devices have been described in the literature. However, as described in Reference 23 and elsewhere, such approaches are either tailored to a specific circuit and constitute clever modifications to such a circuit, or they require that some components such as data converters already exist on the device. Instead, the goal of this section is to describe how the general-purpose functionality of external DSP-enabled test equipment can be emulated on-chip without relying on the existence of certain components inside the DUT. Thus, the circuits described here can be thought of as miniature versions of some of the critical analogue instruments on ATE. Such miniaturisation promises to provide a significant improvement in the number of analogue test channels available for simultaneous operation. Thus, for sufficiently complex devices, many blocks within the devices can be tested simultaneously. Alternatively, multisite testing in which several devices are tested simultaneously can be facilitated since it now does not rely on the limited number of instruments available on the tester. Another goal of this section and the next ones is to describe how providing such flexible test capability on-chip also avoids interconnect-related difficulties and provides much improved correlation between simulation, design verification, and production testing. Improved correlation comes about, of course, because the same measurement instruments and input conditions are used in simulation, design validation and production testing.

Functionally, our proposed integrated test core looks like a fully-fledged generic DSP-based test system (Figure 10.6). It consists of a band-limited arbitrary waveform generator and a periodic waveform digitiser both synchronised using a single clock source. A more detailed view of the components comprising our test system is shown in Figure 10.7, although the clocking system is omitted for clarity. The system consists of two one-bit memory files (referred to as Memory A and Memory B), some simple analogue structures, and a multibit output memory for output data storage. A key feature of this architecture is its simplicity and modularity: an almost all memory (all digital) implementation is used, which allows for faster design times, robustness to process variation, and scalability. The left part of the figure consists of two one-bit memory-based analogue signal generators, one for AC stimulus generation and one for DC voltage generation. The latter is combined with the analogue comparator to perform multibit-resolution digitisation. The following subsections describe the encoding methods for the signal generators and our signal capture method.

Figure 10.6: Block diagram of proposed on-chip test system

Figure 10.7: A more detailed view of the integrated test system architecture

10.5.1 Signal generation (circular memory A)

We synthesise analogue test signals using a short repetitious sequence of digital bits that are chosen to approximate the output of a one-bit ΣΔ modulator when driven by a periodic signal. The concept behind this generation approach was described in References 24 and 25, and it consists of simulating a software model of a high-order noise-shaping modulator and capturing a finite duration segment of its output. Periodically repeating this segment approximates the usually aperiodic infinite-duration output of the ΣΔ modulator. However, as described in Reference 25, in order for the periodic approximation to achieve a high fidelity, the frequency of the input signal to the software ΣΔ modulator has to be harmonically related to the chosen fundamental frequency of the bit sequence. If N is the length of the approximate ΣΔ sequence and F_S is the sampling rate, then the input to the modulator has to be an integer multiple of F_S/N. In fact, the forced periodicity of the approximate ΣΔ output also means that the encoded signal contains only multiples of this same fundamental frequency.

As can be seen, the frequency resolution of this approach, which is defined as the minimum frequency deviation between two simultaneously generated sine waves, is thus F_S/N. Also, the clock-derived frequency synthesis property of this memory-based generator is an important feature that makes it favourable in our application as it guarantees sample coherence with our on-chip circuit-response digitiser. Coherent sampling enables the use of a small number of samples in a DSP-based measurement environment [26].

Since our periodic bit patterns approximate the output of a ΣΔ modulator, general properties of ΣΔ modulation determine the quality of the resulting analogue signals. For example, just like ΣΔ modulators used in data conversion applications, increasing modulator order has the promise of improving in-band SNR [27]. Other factors that determine the performance of ΣΔ modulators include modulator topology and the oversampling ratio (OSR). As for the periodic ΣΔ approximations considered here, these parameters as well as other tools such as the choice of bit sequence length, arbitrary choice of centre frequency, and unconventional stability properties [25] are all available for obtaining the best bit streams for the application of interest. Indeed, the possibility of modifying encoded analogue signal properties through a manipulation of these tools results in tremendous versatility using this approach.

As an example of the quality of signals encoded using this method, Figure 10.8 illustrates the power spectral density (PSD) of a third-order noise-shaped periodic ΣΔ stream. As can be seen, noise due to the one-bit quantisation operation on the input sine wave is shaped out of band in much the same way as would be the case in a ΣΔ modulator. The tonal behaviour of the noise is simply an outcome of the periodic nature of the bit stream. In general, the signal generation operation is completed by filtering out these noise harmonics and reconstructing the original sine wave. A description of the trade-offs involved in the design of the filter as well as applications in which such a filter may or may not be required is included in [28] and is omitted here in the interest of brevity. In a nutshell, the ability to modify the spectral properties of the periodic ΣΔ streams results in fairly relaxed requirements on the analogue reconstruction filter. Rather than designing the filter to match some encoding scheme, we instead shape the spectrum of the programmable streams to match the roll-off behaviour of the implemented filter within the desired test system bandwidth. Alternatively, the device being measured might itself contain a filtering operation as is the case with many of the building blocks in a wireless transceiver circuit, and an additional filter is not required at all in such a scenario. We are of the view that separating the filter design in this case from the synthesis of the overall test system allows for a more flexible and modular solution. Coming back to Figure 10.8, we specifically show a low-order example in this figure since low-order noise shaping relaxes the requirements on the order of any analogue filter that reconstructs the encoded in-band signal. Even with such a low order, high spectral purity is achieved using only a 1024 bit long memory. Examples of high-frequency analogue signal generation through the use of bandpass modulation in encoding the periodic ΣΔ streams [25] are illustrated in Section 10.6.

Figure 10.8: Frequency spectrum of a periodically repeating ΣΔ modulated sequence encoding a single sine wave. The sequence length in this example was 1024

10.5.2 Signal digitisation (circular memory B and comparator)

Signal digitisation is performed using the combination of circular memory B, its associated passive RC filter, and the voltage comparator. The combination of these blocks in the manner shown in Figure 10.7 enables us to achieve multibit analogue waveform digitisation using compact and simple hardware. This is done by exploiting the periodicity of the analogue signal under test (which is enforced in our architecture) and making multiple comparison passes over progressive periods of this signal. Referring to Figure 10.9, the complete digitisation process proceeds as follows [29]. First, the reference input to the comparator is set to a constant voltage to which all samples of a unit test period (UTP) of the analogue waveform are compared. This voltage of course represents one of the quantisation levels of the overall A/D conversion. Once all comparisons to this level are made (stored in memory), the voltage at the reference input to the comparator is incremented to the next level, and the process repeats. As an alternative, we can use a binary search algorithm over progressive runs of the UTP [30], but the principle of successively approximating the analogue waveform over multiple UTP runs remains the same.

Figure 10.9: Exploiting the periodicity of the input signal to perform multiple digitisation passes. UTP = Unit Test Period

The way the reference input to the comparator is defined in our system is through the combination of memory B and its associated averaging filter. Specifically, accurate DC reference levels are encoded in memory B, again using a periodic sequence of digital ΣΔ modulated bits whose average equals the desired DC level [28, 31]. By encoding an average signal in a periodic rectangular waveform, extremely high linearity is achieved. This is an important requirement in our application since the linearity of the overall on-chip digitiser is determined by the linearity of the reference inputs to the comparator. In other words, the combination of the comparator and a variable reference generator is similar in principle to a successive-approximation A/D converter, although we rely on subsampling to enable the digitisation of high-frequency signals. One of the linearity limitations for successive-approximation A/D converters is the non-linearity of the DC reference generator (D/A converter). The reader is referred to Reference 28 for some guidelines on the software generation and optimisation of periodic noise-shaped bit sequences for DC level generation. As for the averaging filter that is used to extract the encoded DC levels, only a passive on-chip filter is implemented [28, 31], and the reason is to maximise robustness to process variations and to minimise design effort. For guidelines on the design of the passive filter, the reader is referred to Reference 32.

It should be noted that the digitisation algorithm described here relies primarily on the proper synchronisation with the excitation system. In each comparison pass, the comparator is expected to see the exact same samples of the test signal as it did in the previous passes. This is easily achieved using the bit stream generation approach, since all the generated DUT stimulus tone phases are well defined with respect to the sampling clock, F_S. On another note, the clock speed of the periodic bit stream generators is generally faster than the comparison speed of typical integrated analogue comparators. Under these circumstances, a sample-and-hold (S/H) circuit (which can track and sample very fast signals) can be inserted at the corresponding input of the comparator to receive the signal from the circuit under test. The addition of such a circuit allows the comparator to take multiple master clock cycles (1/F_S) to arrive at a decision about the relative magnitudes of its two input signals without compromising the effective sampling rate of the digitiser. The only requirement is that the ratio of F_S and the comparator clock frequency has to be a prime relative to the total number of samples in a test period, N, which is the same as the requirement for coherent sampling [28]. Similarly, when broadband signal digitisation is sought, the comparator clocking system can be modified further according to the methods in [28] to result in a high-bandwidth and flexible on-chip measurement solution.

Processing of the comparator output is done using a multibit memory (Figure 10.7) that is the same length as that of memory A and that is initialised to zero at the beginning of a measurement run. For each comparison pass, the bit stream generators continuously circulate their contents to output the analogue stimulus and the appropriate reference level, respectively. For each circuit response sample, the corresponding memory location is incremented or left unchanged, depending on whether the comparator output (for the current DC level) was 1 or 0. At the end of the digitisation process, each memory location contains an integer count representing the quantisation level for the corresponding sample (i.e. a thermometer code).

10.5.3 Self-checking

In order to increase the confidence in the on-chip test results, it is important for the test core to at least provide a way of checking whether it works or not. The number of checks that can be performed on the test system depends on how much time and effort the final system on chip (SOC) integrator is willing to spend. For example, referring to Figure 10.10a, the following simple check can locate catastrophic failures in the comparator. The reference input to the comparator is set to mid-rail, and the AC bit stream generator output is fed directly to the comparator input. As such, the comparator simply looks like a digital latch, so a bit-for-bit comparison between the input bit stream and the stream coming out of the comparator can be performed. Note that this is a test that can be performed completely in software using digital techniques. Moreover, this test automatically uncovers stuck-at faults in the circular memory structures.

The above tests could be sufficient for some applications, and the comparator can then be assumed to function properly and can be used to check other circuits or the circuit under test (CUT). Alternatively, more rigorous testing of the comparator resolving power can be done as follows. Another replica of the DC generator can be implemented in hardware and connected to the ‘signal’ terminal of the comparator, while the usual DC generator is connected to the ‘reference’ input. This way, slightly differing DC signals can be applied at different common-mode levels in order to verify (to the extent to which the DC sources are matched) the resolving power of the comparator under different signal conditions (Figure 10.10b). Replicating the DC generator seems to be feasible because it consists of a mostly digital implementation and thus scales favourably with technology. Again, this test can also be performed in software, and it provides for a quick and cheap relative measure of the comparator resolving power.

Figure 10.10: (a) Converting the comparator into a digital latch to verify functionality. (b) Replicating the DC generator allows for a quick method of sweeping comparator terminals

If an analogue filter is implemented as part of the test core, then it too will have to be characterised in order to maximise the available test signal bandwidth. Referring to Figure 10.11, now that the comparator is verified, the implemented filter magnitude and phase response can be measured using our integrated capture system using a multitone stimulus signal [6]. The filter response can then be compensated for in the bit stream generation phase. Other types of tests can also be performed on the filter before the overall test system can be used to verify the other integrated analogue circuits. For example, in a manner similar to [33], a model of the non-linearity introduced by the filter can be created, and its effects can be cancelled in software when, say, the non-linearity of the circuit under test is being verified.

Figure 10.11: Test core bypassing CUT in order to measure the analogue reconstruction filter (clocking system not shown for clarity). The response (b) to a multitone signal (a) can be captured using an integrated digitiser (c) in order to predict filter behaviour