Acknowledgements

We are pleased to acknowledge support for the research described herein from the following sources: DARPA NeoCad Program under grant N66001-01-8919; Semiconductor Research Corporation grants 2001-HJ-926 and 2003-TJ-1093; National Science Foundation contracts CCR-0086032, CCR-01200255 and MRI-0116281, and grants from the National Science Foundation Center for the Design of Analog/ Digital Integrated Circuits (CDADIC), Texas Instruments, National Semiconductor, and Intel.