Chapter 9: Parasitic-Aware RF IC Design and Optimisation

Kiyong Choi, Jinho Park, David J. Allstot

9.1 Introduction

Based on the principles of radio communication theorised by Maxwell in 1862, the wireless communications industry has grown exponentially during the past few decades. Nowadays, almost everyone owns at least one wireless communications product such as a television, radio, cellular phone, cordless phone, pager, wireless modem, wireless computer peripheral, etc. Because of the burgeoning popularity of wireless communications, research is ongoing to develop small-size, lightweight, low-cost, and highly power-efficient products. Moreover, consumers continually demand less expensive and more portable personal communications devices with ever increasing functionality. Consequently, intense worldwide research is focused on the design of RF communication circuits that can be integrated with both analogue and digital subcircuits in CMOS system-on-chip solutions.

Two major constraints in the design and optimisation of RF frontend circuits in fine-line CMOS technology are active devices that are inferior to their GaAs and SiGe counterparts, and low-quality parasitic-laden passive components owing to the use of lossy silicon substrates. To overcome these drawbacks, the parasitic-aware synthesis paradigm has been developed. Simulated annealing is one of the key algorithms used in the parasitic-aware CAD design and optimisation methodology.

Unlike in baseband circuits, the parasitic effects are severe in high-frequency circuits. In the case of baseband circuit design, minimising parasitics is usually sufficient. However, the parasitics must be carefully modelled and considered as part of the design process in high-frequency circuit synthesis. For example, if an RF circuit is first designed without considering parasitics, simulations show that it often loses most of its performance when parasitics are subsequently included. On the other hand, if parasitics are considered as part of the design, it is difficult to find an analytic solution by hand. The parasitic-aware synthesis paradigm has been developed to address these difficulties.

One of the burning issues in optimisation is how best to consider process, voltage and temperature (PVT) variations. Circuit simulation with PVT variations is very time consuming because Monte Carlo methods are normally required, and it is difficult to make them part of the optimisation process. Consequently, the analysis of PVT variations as part of a post-optimisation process will be discussed.

In this chapter, parasitic-laden inductor modelling is first discussed. The conventional simulated annealing algorithm is then described and compared to classical gradient descent optimisation techniques. Finally, the shortcomings of the conventional simulated annealing algorithm are addressed. An innovative adaptive simulated annealing algorithm is proposed to improve upon the conventional algorithm. Post-optimisation PVT variation analysis is discussed, and two high-frequency circuit examples show that parasitic-aware CAD optimisation is essential in RF circuit design.

Before discussing the CAD optimisation techniques, compact inductor models are briefly reviewed in order to understand the parasitics associated with on-chip spiral inductors.