8.4 Recent progress in RF CMOS PA design

Research in the area of power amplifiers is divided into two main categories: the design and monolithic implementation of power amplifiers and the integration of linearisation techniques. While the implementation of a complete transceiver was the focus of many publications ([23–26]), the power amplifier was included in only two of the reported CMOS wireless transceivers [23, 26]. The first CMOS power amplifier that was reported targeted the 900 MHz ISM band [27] delivering output power from 20 μW to 20 mW using a3-V supply, and implemented in 1 μm technology. The measured drain efficiency with the inductors included on-chip was 25 per cent. No input matching was included since the power amplifier was integrated in a complete transceiver [23]. The output-matching network was implemented off-chip. An extra fabrication step was used to remove the substrate beneath the inductor to improve the quality factor.

In Reference 28 a 1 W BiCMOS PA was reported. The design involves a negative resistance stage to boost the gain. The reported power added efficiency (PAE) is 30 per cent usinga5V supply. External inductors were used as part of the interstage matching network, with the output matching network completely off-chip. Measurement results are reported for a chip-on-board die. While BiCMOS is capable of supporting other RF transceiver functions and is a strong candidate as a low-cost technology for realising a single-chip radio, the reduction in performance of a BiCMOS PA compared to GaAs PA was evident in this paper.

Many publications anticipated that CMOS would be limited only to low-power, low-performance applications. In Reference 29a1W, 2.5-V supply monolithic power amplifier was reported. The PA targeted NADC standards (824–849 MHz). A gain of 25 dB was achieved through three gain stages (operating in class A, AB and C), with the output stage operating in class D (transistor is used as a switch). The power amplifier had a measured drain efficiency of 62 per cent and a PAE of 42 per cent. It did not have a high degree of integration since the output-matching network was implemented off-chip. Bond wires are also used as part of the interstage matching network.

The use of non-linear power amplifier classes has been limited to low-frequency operation until a recent publication explored the possibility of using class E power amplifiers in the 900 MHz band.

In Reference 12 a fully integrated, yet GaAs MESFET implementation of a class E PA was reported. This non-linear power amplifier outputs 250 mW at 835 MHz with power-added efficiency (PAE) of 50 per cent in a 2.5 V system. A class F amplifier was used as a driver stage to generate the required square wave input driving signal. Bias voltages were applied externally but all matching networks were included on-chip. This paper illustrated the advantages of operating at class E rather than classes C, B or F, considering the fact that it has higher optimum load and higher PAE under low-voltage operation.

Class E power amplifiers have generated wide interest after the previously mentioned publication due to the inherent high efficiency. In Reference 1 a 1.9 GHz, 1 W class E PA was implemented in 0.35 μm CMOS technology using a2 V power supply. The input driving requirement of the output stage was greatly reduced by employing the concept of mode-locking in which the amplifier acts as an oscillator whose output is forced to run at the input frequency. The output-matching network was off-chip, and all inductors included were bond wire inductors. The measured PAE using chip on-board packaging is 48 per cent. The drawback of the mode-locking (positive feedback) technique is that the PA is prone to locking onto interfering signals picked up by the antenna from adjacent mobile users.

While the trend in most publications is to adopt non-linear power classes (class D [29], class E [1, 10, 21, 30], and class F [5, 22]) to implement high-efficiency and high-power amplifiers, the continuous decrease in the voltage breakdown of transistors for deep-submicron technologies makes the use of class E amplifiers more difficult. Class F emerges as a possible solution in this case [1, 2]. However, modern communication standards employ non-constant envelope modulation techniques that require linear power amplifiers, which means that either added linearisation circuitry would be required or traditional linear power amplifier classes are used [2, 31]. A sample of the publications listed in Table 8.2 shows that even though the inductors and capacitors that may be realised in CMOS technology are not suitable for high-performance RF circuits, CMOS transistors still have adequate gain till 2 GHz, allowing the design of low-cost hybrid 1 W amplifiers. The real merits of CMOS PAs lie in the potential for future integration. While the feasibility of a stand-alone CMOS PA does not imply its compatibility in a larger system, integration issues will rely on system, circuit and layout solutions rather than design of individual blocks. In the linearisation area, few papers have been published dealing with monolithic implementation [19, 32], while most of the published work was focused on system simulations and discrete implementations [33, 34].

Table 8.2: Example of reported CMOS power amplifiers
Reference	Technology (μm)	Frequency (MHz)	P_out (dBm)	PAE (%)

27	1	900	13	30–40
29	0.8	824–849	30	42
10	0.25	900	29.5	41
1	0.35	1900	30	48
2	0.25	1950	29.2	27
31	0.35	1730	30.4	45
5	0.25	1400	24.7	43
22	0.2	900	31.7	43

In Reference 32 a phase correcting feedback system to reduce the AM to PM distortion of class E PA used in the NADC standard was presented. The system employed a limiting amplifier, a phase detector, and a phase shifter, all operating at 835 MHz. In order to reduce the phase error in the output caused by the class E amplifier, the output and input phases of the amplifier were compared and an error phase signal was generated. The error signal was applied to a phase shifter at the input of the PA. The phase correcting feedback system reduced the phase distortion from 30 degrees to 4 degrees and consumed 21.5 mW while the PA delivered 500 mW.

In Reference 19 a full monolithic CMOS implementation of the envelope elimination and restoration linearisation system that improves linearity of an efficient PA was fabricated in a 0.8 μm CMOS process. A delta modulated switching power supply was employed to extend the modulation bandwidth to fit that of the NADC. The linearisation system improves the overall efficiency from 36 to 40 per cent while increasing the maximum linear output power from 26.5 dBm to 29.5 dBm. Compared to the usual discrete implementation of EER systems used in high-power basestations, this design is amenable to integration in a low-cost CMOS technology and makes linearisation affordable to handsets.

In Reference 21 a 20 dBm power amplifier for linear amplification with non-linear components (LINC) transmitters was reported. An open loop linearized PA was realised by combining two non-linear class E amplifiers. The paper deals with a portion of the transmitter, not the whole system, and achieves 35 per cent of power added efficiency under linear operation.