7.5 Conclusions

This chapter has demonstrated the potential of using standard digital state-of-the-art submicron CMOS technologies to realise critical radio frequency integrated circuit building blocks, operating in the gigahertz range. In order to cope with the trend of technology down-scaling, and the continuous decrease in the supply voltages of digital circuitry, the work focused on circuit architectures and topologies suitable for operation from 1 V supplies and lower, while delivering performances comparable, and in some respects, better than similar circuits requiring higher supply voltages.

In particular, a folded cascode LNA structure was shown to be very versatile. It allows gain tuning without any additional circuit complexity or performance degradation. Similarly, a very low voltage VCO structure that maintains all the features of the conventional complementary differential LC VCO circuit, while operating from a much lower supply, and providing a wider tuning range, was proposed. Finally, a complete 5 GHz receiver frontend that was optimised for operation from a supply voltage as low as 0.8 V, and that features high image rejection, was presented.

All the architectures and circuits proposed were demonstrated through measurements from different IC prototypes. It should be noted that the CMOS technology we used did not offer any special RF oriented devices, such as thick metal layers, etc. In practice, that would be the case, suggesting that the performances reported in this chapter are expected to be further improved. Finally, this chapter discussed practical integrated inductor design guidelines and layout techniques, which are both crucial for the success of any RF circuit implementation.