Chapter 7: Low-Voltage Integrated RF CMOS Modules and Frontend for 5 GHz and Beyond


Mourad N. El-Gamal, Tommy K. Tsang

7.1 Introduction

The growing number of users and the demand for high-speed wireless communications has motivated designers to move from the 1–2 GHz range towards higher frequency bands. Recently, new standards in the 5 GHz range for wireless local area network (WLAN) applications have been defined, such as the IEEE 802.11a standard for the FCC unlicensed national information infrastructure (U-NII) band in the US, and the high performance radio LAN (HIPERLAN) standard in Europe.

Traditionally, radio frequency integrated circuits (RFICs) were implemented in GaAs or SiGe bipolar technologies, because of their relatively high unity gain cutoff frequencies fT (i.e. >65 GHz) and their superior noise performance. However, as the minimum feature size of CMOS devices decreases, the fT of the transistors continues to improve to the point where it is becoming comparable to those of GaAs and SiGe processes. Deep-submicron CMOS devices with fT's exceeding 100 GHz and minimum noise figures (NF) less that 0.5 dB at 2 GHz have been demonstrated [1]. Because of these promising RF performances, together with the advantages of low cost and ease of integration with baseband digital circuitry, CMOS is becoming a viable alternative for RF applications, with continuous efforts towards implementing higher frequency circuitry operating from lower supply voltages (e.g. [2–15]).

This chapter starts by introducing a CMOS low noise amplifier (LNA) architecture suitable for operation from sub-1 V supplies. Experimental results from several fabricated prototype chips are presented to demonstrate the versatility of this topology. Namely, the first prototype operates at a centre frequency of 5.8 GHz, with gain and frequency tuning capabilities. The second and third prototypes were optimised for future RF applications, operating at higher carrier frequencies of 8–9 GHz, also featuring gain control. Implemented in a standard 0.18 μm CMOS process, all circuits exhibit a power gain of greater than 12 dB with a noise figure as low as 2.5 dB, when operating from a 1 V power supply. All implementations have a gain tuning range of over 10 dB, and can operate from a supply voltage as low as 0.7 V. The LNAs use no off-chip components, allowing for a simple and robust integration.

The chapter then proceeds with introducing a new LC-based oscillator structure, which also enables operation from very-low supply voltages (0.85 V), while being suitable for high-frequency RF applications. Two 0.18 μm CMOS VCO prototypes are reported. The 8.7 GHz VCO operates from a supply voltage of 0.85 V, consumes 6 mW, and exhibits 100 dBc/Hz phase noise at a 600 kHz offset. The 10 GHz prototype operates from a supply voltage of 1 V, consumes 9 mW, and has 98 dBc/Hz phase noise at a 600 kHz offset. A tuning range of 400–450 MHz is achieved without using varactors.

Finally, in order to demonstrate the potential of using CMOS for low-voltage, high-frequency applications, the chapter concludes with the presentation of a 5 GHz receiver frontend operating from a 0.8 V supply.




Wireless Communication Circuits and Systems
Wireless Communications Circuits and Systems (IEE Circuits, Devices and Systems Series 16)
ISBN: 0852964439
EAN: 2147483647
Year: 2004
Pages: 100
Authors: Yichuang Sun

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