4.6 Reconfigurable universal transceivers using FPAAs

4.6 Reconfigurable universal transceivers using FPAAs

Universal transceivers are required to meet various wireless communication standards. Universality requires that the transceivers should be programmable and reconfigurable. FPAAs may be used to achieve different functions, for example, different bandwidths, in future ubiquitous transceivers. This section addresses these issues.

4.6.1 Universal transceivers for different standards

FPAAs can be used for development or prototyping purposes. They can also be used in many other areas as mentioned in Section 4.2.6. One example may be to use FPAAs in multistandard transceivers [61–65]. Due to its programmability and reconfigurability, using the FPAA in the analogue baseband or IF stage or even RF frontend, it is possible to obtain universal transceivers that support all the standards for mobile communications in the world. The expanding growth of wireless communications has led to the proliferation of different standards. The market demands low-cost, low-power and small form-factor devices. Different second generation (2G) mobile systems have effectively utilised digital technology to increase capacity, improve reliability and lower system size and cost. However, they were developed to handle voice and low data rates and are not capable of handling traffic of high data rates like multimedia applications. Thus third generation (3G) wireless systems have emerged, which aim to integrate multiple applications, combined from consumer electronics, computer and communication markets. Applications such as audio/video, interactive video services, telephoning, e-mail, and internet access with real-time image transfer are expected. To achieve compatibility and global roaming, 3G-enabled transceivers are required to operate in different modes with multistandard support. The use of WCDMA (Wideband Code Division Multiple Access) in 3G to achieve high data rates demands higher channel bandwidth. Thus the analogue frontend must be redesigned to handle wider bandwidth with efficient power consumption. To avoid such redesign, it is desirable to have an analogue frontend with programmable bandwidth for multistandard support.

4.6.2 Reconfigurable transceivers using FPAA

The ultimate aim is to produce a single-chip transceiver, which can be dynamically configurable to support many air interfaces, quality of service (QoS) requirements and applications. As discussed above the best way to achieve this is to use reconfigurable hardware, both in the analogue and digital domains of the transceiver. Until now the flexibility provided by reconfigurable hardware has only materialised in digital domain. There have been attempts to move the ADC into the RF stage of the receiver to leave only the anti-aliasing filter in the analogue domain. In order to achieve this, the ADC must digitise the complete incoming RF signal bandwidth. Coping with a signal of such large bandwidth and high dynamic range is a difficult task for ADCs. So this type of ideal software radio may not be possible in practice in the foreseeable future. Positioning the ADC after the down conversion to the IF frequency of the receiver, but before the IF processing, can solve the problem. Here the IF signals can be processed digitally in the digital frontend (FPGA). The benefit of using a digital frontend is the very good flexibility because of DSP and increase in system versatility. On the other hand, it also increases power consumption, and high sample rates typically require the use of complex time-shared hardware and increased ADC dynamic range. There are many inherent benefits in implementing the IF stages of the receiver using analogue circuits and techniques, such as smaller silicon area and reduced power consumption, but in doing this we remove the flexibility required by the multistandard receiver. Using reconfigurable analogue devices we could solve this problem.

The radio receiver design using the FPAA to improve the IF stage performance and reconfigurability is shown in Figure 4.17. There are three possible IF structures: high IF, low IF and zero IF. For zero IF, FPAAs using switched-capacitor and active RC techniques can be used and with current technology, low-IF stages can also be implemented using FPAAs such as those based on the MOSFET-C and OTA-C technique. For a high-IF stage, the OTA-C FPAA may be the only candidate. Note that the zero-IF stage requires lowpass filters and the high-IF stage uses bandpass filters. The low-IF stage may use either lowpass or bandpass filters. From the low power and small die size viewpoints, single amplifier filter structures have been used in some applications [64, 65]. On-chip tuning of high-Q, high-frequency bandpass filters is a big challenge for high-IF design and such tuning circuits must be integrated into the FPAA [39].

Figure 4.17: Radio receiver with analogue frontend

Fully reconfigurable receivers may also use an FPAA for the RF frontend. With this fully reconfigurable receiver, software and hardware reconfigurability can be achieved in the RF, IF, as well as baseband. But current FPAAs are still far away from meeting RF requirements.

Finally, the concept of the FPMA may be used, which combines the FPAA (analogue frontend), ADC (interfacing) and FPGA (digital frontend) together, as shown in Figure 4.18.

Figure 4.18: Radio receiver using FPMA

Single-chip transceivers require the use of CMOS technology, but the design of analogue and RF circuits in digital CMOS technology entails many difficulties that challenge researchers. Further to transceivers on a single chip, the future market also requires a transceiver on a programmable chip, which will almost certainly see the application of the FPAA and FPMA. This will present a fascinating challenge to FPAA researchers and designers.