4.4 Continuous-time CMOS OTA-C FPAA for high frequencies

4.4 Continuous-time CMOS OTA-C FPAA for high frequencies

For low-frequency analogue frontends in signal processing systems, the FPAA using the continuous-time MOSFET-C approach can achieve very good performance. But for high-frequency operations, the OTA-C technique is the best choice. Using the OTA with programmable transconductance (g_m), and the programmable capacitor array, it is possible to build different circuits for various high-frequency applications.

4.4.1 Programmable OTA

The simplified schematic diagram of the OTA based on two cross-coupled differential MOS pairs and digitally programmable current mirrors is shown in Figure 4.7 [18, 19]. Using the standard square-law model for MOS devices and assuming that the current gains of the programmable current mirrors are all equal to A, the output current can be derived as

where K = 0.5μC_oxW/L is the transconductance parameter of transistors M1–M4, having the same W/L ratios, V_b is the voltage of the floating DC source, Vs = V_in+ − V_in− is the differential input voltage and g_m is the overall transconductance of the OTA circuit.

Figure 4.7: Simplified schematic diagram of the CMOS programmable OTA

In order to be suitable for a wide range of OTA-C filter designs, it is necessary that the transconductance of the OTA should be adjustable over a wide range. From (4.1) it can be seen that two methods can be used to change the transconductance g_m. One method is to tune the floating bias voltage V_b by an analogue voltage V_ctrl. The other is to make the gain A of the output current mirrors programmable in a digital way.

A current mirror of programmable gain can be realised using the well-known high-compliance current mirror structure, using 31 identical output stages as shown in Figure 4.8 [19]. The output current I_out is the sum of the currents flowing through individual output stages. As can be seen from Figure 4.8, the output stages are connected in five groups of 1, 2, 4, 8 and 16 stages that can be simultaneously switched on or off by the appropriate switch S_i where i ={1, 2, 4, 8, 16}. Using n stages, the output current I_out can be set to a value between I ^min_out = I_in and I ^max _out = nI_in with resolution ΔI_out = I_in. Only five output groups (five bits) were implemented due to the huge number of MOS devices required for the most significant bits.

Figure 4.8: Simplified diagram of programmable current mirror array

In practice, every switch Si must be accompanied by another switch Si, which can short-circuit the gate of the transistor Mia to ground. This is necessary for discharging the parasitic capacitance C_gs of the transistor Mia and stopping the current I_i flowing. The cascaded current mirror structure is used to achieve high output resistance.

The complete circuit diagram of the OTA including the floating voltage source and common mode feedback circuit can be found in [19]. Simulation and chip test results in CMOS show that the OTA has a transconductance tuneable/programmable in a wide range of 700 times using both Vctrl and digital tuning and a 3 dB bandwidth larger than 20 MHz.

4.4.2 Programmable capacitor array

The structure of the programmable capacitor array is shown in Figure 4.9 [19]. It consists of five capacitors C₀–C₄ and switches S_C0–S_C4. The branch of capacitor C₀ and switches S_C0 represents the least significant bit (LSB). Each branch is built of an appropriate number of LSB branches (connected in parallel).

Figure 4.9: Programmable capacitor array

Switches are made using MOSFETs of width high enough to achieve the phase of a capacitor in the range −90 1 for frequencies up to 10 MHz. The equivalent capacitance of the capacitor array can be expressed as

where b_n ∈{0, 1}, b_n is equal to 1 when switch S_Cn is on and equal to 0 when S_Cn is off, C_ON and C_OFF are the capacitances of the LSB capacitor when switches S_C0 are in ON and OFF modes, respectively, while C_PAR is the parasitic capacitance of connections when all the switches are off.

4.4.3 Configurable analogue block using programmable OTAs and capacitors

Figure 4.10 [19] shows a versatile CAB consisting of one programmable fully differential OTA, one programmable capacitor C_EQ and a set of switches S₁–S₁₂. The switches are placed in such a way that the OTA can be connected with or without the capacitor. It is also possible to pass the signals of other CABs through the switches situated at the top and the bottom of the CAB. Switches S1 and S2 allow connection of the input to the OTA directly or in an inverse way. To program the CAB, a control word of length 22 bits must be specified (OTA: 5 bits; capacitor: 5 bits; switches: 12 bits), as well as the voltage V_ctrl controlling the transconductance of the OTA through Vb. The control word is stored in a shift register, while the voltage Vctrl is supplied from the external automatic tuning circuit. This CAB can be configured to perform functions like addition, subtraction, amplification, attenuation, integration and filtering of signals of frequencies from several kHz up to a few MHz.

Figure 4.10: Structure of OTA-C CAB

4.4.4 Fine tuning of parameters

The proposed FPAA includes three inputs and three outputs. This enables the implementation of up to three independent filters or other circuits working concurrently. Tuning of filters is based on small parameter differences between components inside the chip, so setting the reference integrator (or other reference circuit containing OTAs and Cs) to the desired gm/C ratio will reflect on the filter characteristic frequency. The accuracy of such tuning is dependent on how precisely the desired gm/C ratio can be achieved and the technology used. Practical implementations provide 0.1–5 per cent accuracy [19].

Figure 4.11 presents the block diagram of the tuning circuitry used during testing of the chip [19]. The upper part is the reference circuit consisting of four lossy integrators. The lower part is a tuned filter. All OTAs in the reference part as well as in the filter are identical and have the same value of control voltage Vctrl. Comparison of an integrator's phase delay with its desired value gives a signal which can be used in the manual or automatic correction of Vctrl.

Figure 4.11: Simplified schematic diagram of the tuning circuit

4.4.5 FPAA using CABs and its application in OTA-C filter design

With the above building blocks and discussions, we can now proceed with the design and implementation of FPAAs. We will present an FPAA with 40 CABs and demonstrate an application example of a high-order bandpass filter.

4.4.5.1 FPAA using 40 CABs

The FPAA used for implementation of filters is presented in Figure 4.12 (block diagram) and Figure 4.13 (die photograph) [19]. It consists of 40 CABs from Figure 4.10 positioned in eight columns and five rows. Additionally three OTAs o1–o3 act as signal buffers. Input signals are delivered through lines i1, i2 and i3. Because of this, up to three different filters can be implemented simultaneously. The transconductance parameters of all the OTAs are controlled by the external voltage Vctrl and through digital switching of the output current mirrors. While the voltage Vctrl is common for all the amplifiers in the array, it is still possible to set the transconductance of every OTA separately by setting the gain of the OTA's current mirror. The FPAA was physically implemented in the CMOS process through MOSIS. Programming of the FPAA is performed through serially shifting digital words of 880 bits into programming registers.

Figure 4.12: Structure of OTA-C FPAA. Bold lines represents active connection, which realises a sixth-order bandpass filter with tuning circuirty

Figure 4.13: Layout of matrix of 5 8 CABs in Figure 4.12

4.4.5.2 Implementation of a leap-frog bandpass OTA-C filter using FPAA

A sixth-order bandpass filter with centre frequency f₀ = 60 kHz and passband BW = f₀ is designed based on simulation of a passive LCR ladder [19]. The schematic diagram of the filter is presented in Figure 4.14. The placement of Figure 4.14 in the FPAA resources is shown in Figure 4.12. The calculated values have been rounded to the nearest values realisable in the FPAA. The capacitor's values also include the parasitic capacitances of switches and connections. Adjusting the analogue voltage Vctrl can change the centre frequency of the filter about 22 times. In Figure 4.12, the upper part (i.e. the first and second row of CABs: A1–H1 and A2–H2) includes the tuning circuitry described in Section 4.4.4. Additionally, in the practically implemented tuning circuit in Figure 4.12, OTAs E1 and E2 have opposite transconductance values, so the signals actually observed at the outputs o1 and o2 should have exactly the same phase (not −180 ). The frequency fⁱ¹ of the reference input signal can be calculated.

Figure 4.14: TA-C realisation of sixth-order bandpass filter

The filter was implemented in the structure of the FPAA. Measurements were taken after applying a signal of frequency f_i1 to the input i1 (Figure 4.12) and manually setting the value of the control voltage V_ctrl so that signals observed at the outputs o1 and o2 were in exactly the same phase. This tuning technique was described in Section 4.4.4. Comparing with the ideal characteristic, the filter exhibits no more than 1 dB error in the range 2–200 kHz. Switches placed in the paths conducting relatively large currents are the main cause of this error.