3.2 Low-noise fully differential voltage buffer

3.2 Low-noise fully differential voltage buffer

The well-known Sallen–Key (SK) families of filters are attractive as they utilize a single voltage buffer to implement cascadable continuous time filter sections. Most high-performance analogue integrated circuits incorporate fully differential signal paths. This is because fully differential operation improves the performance of mixed analogue/digital systems in terms of supply noise rejection, dynamic range and harmonic distortion. To achieve a high dynamic range, fully differential version of SK filters, a fully differential buffer (FDB) circuit with low noise and high linearity is required. The required fully differential buffer cannot be designed using a regular op-amp. It is necessary to find a CMOS circuit that will lead to the realisation of a fully differential buffer with low power consumption and low flicker noise.

3.2.1 Differential difference amplifier-based fully differential buffer

In this section we present a class AB CMOS fully differential buffer circuit that provides low standby current consumption, high current driving capability and low input referred noise.

The proposed fully differential buffer is achieved using a fully balanced version of the differential difference amplifier (DDA) [2, 3]. The DDA is a five-terminal device as shown in Figure 3.1a. It has two differential input ports (V_pp −V_pn) and (V_np−V_nn), rather than two single-ended inputs as is the case in the conventional op-amp.

Figure 3.1: Single-ended DDA symbol: (a) symbol, (b) class AB realisation

The output of the DDA can be expressed as

where A_o is the open-loop gain of the DDA. Analogous to a traditional op-amp, when negative feedback is applied the differential voltages of the two input ports become equal:

As the finite open loop gain A_o decreases, the difference between the two differential voltages increases. Therefore, high open-loop gain is required to improve performance.

3.2.2 MOS realisation of a fully differential DDA

CMOS realisation of the DDA is shown in Figure 3.1b. Like an op-amp, the DDA mainly consists of two stages: a differential-input transconductance stage (differential amplifier with active loads) and a second gain stage (common-source amplifier with an active load). However, the DDA uses two differential pairs to implement the two input ports. For low-power operation and high current driving capabilities, a class AB output stage has been employed instead of the class A counterpart. The two differential pairs convert the two differential voltages into two currents that are subtracted, converted into a voltage by the active load, and amplified by the second stage.

A compensating capacitor(C_c) and resistor (R_c) are employed to ensure stability. Arail-to-rail low power out put stage is incorporated. It consists of transistors M7–M10 and biasing transistors M14 and M15. In the absence of input signals, no current is withdrawn from the output terminal. The currents of M9 and M10 are set equal to a small standby current (I_SB). However, when the circuit is supplying current, M9 will be fully conducting while M10 will be almost off. Similarly, when the circuit is sinking current, the current of M10 will dominate and that of M9 will be negligible. A fully balanced DDA (FBDDA) can be designed in much the same way as a conventional op-amp.

Figure 3.2 shows the circuit diagram of the fully balanced DDA. The circuit provides two balanced outputs (V_op =−V_on) that are centred about a well-controlled common-mode voltage level. A CMFB circuit is needed to establish the common-mode output voltage, and without it the common-mode voltage output would drift. The CMFB circuit determines the output common-mode voltage and controls it such that it is equal to some specified voltage (usually mid-rail) even in the presence of large differential signals. When dual power supplies are used, V_cm is set to zero. The CMFB circuit used in Figure 3.2 consists of transistors Mc1–Mc7 in addition to two resistors (R_cm) and two capacitors (C_cm).

Figure 3.2: The fully differential DDA CMOS realisation

3.2.3 Wide-range low-noise FDB based on the DDA

The input differential range of the DDA is determined by the valid area of operation of the differential pairs at the input ports. It is well known that the profile of the differential output current (I_D) of a differential pair versus its differential input voltage (V_d) can be expressed as:

where I_o is the tail current and K is the transconductance parameter of MOS transistors. Operation of the circuit is valid as long as I_D is proportional to V_d, in other words, transistors carry a current or . Outside this region, either current of the differential pair is zero. Therefore, to maintain a wide input and output swing, feedback should be applied in such a way that it forces V_d to have a small value which is very close to zero. In general, negative feedback from the outputs of the DDA to two of its inputs can be achieved in four ways as demonstrated in Figure 3.3. Since the DDA is symmetrical these four combinations can be reduced to two categories. The first category, Figure 3.3a, b, exhibits negative feedback to the same differential pair while the second, Figure 3.3c, d, comprises the feedback to both differential pairs. The first category behaves similar to the DDA since the differential pair, which has no feedback applied to it, will not exhibit a virtual short between its inputs. The second category of circuits will behave like an op-amp because the feedbacks are applied to each of the differential pairs, and hence each pair will exhibit a virtual short between its inputs. Therefore, both differential pairs will operate near V_d = 0, and g_mn(W/L)_n can be designed as large as desired to achieve low noise, high input range, and low distortion simultaneously. Simulation of the DC transfer characteristics indicates that the circuit of Figure 3.3c has the widest linear input differential range for β = 1.

Figure 3.3: Negative feedback combinations

The other major design factor that determines the performance of the DDA-based buffer is noise. A MOS transistor typically generates two types of noise: flicker (1/f) noise and thermal noise [4]. It can be shown that thermal and flicker input referred noises of the proposed FDB are given by:

where K is Boltzmann's constant (1.38 10⁻²³ JK ⁻¹), T is the temperature in kelvin, g_mn = g_mi(i = 1 to 4), g_mp = g_m5 = g_m6 =g_mc1 = g_mc2 are the small signal transconductances of the MOS transistors, K_n and K_p are the flicker noise constant for the NMOS and PMOS transistors, respectively, W and L are the width and the length of the transistors, μ_n and μ_p are the carrier mobilities, C_ox is the gate oxide capacitance per unit area, and f is the frequency. It is clear that the transconductance (g_mn) of the differential pairs should be made as large as possible to minimize thermal noise. Also, increasing the widths of the differential pair transistors clearly minimizes 1/f noise. Moreover, it can be shown that the flicker noise exhibits a minimum for an optimum L_n. This is because L_n appears in the numerator and the denominator of the flicker noise equation. The optimum L_n is given by:

Simulation results show that the profile of the input referred noise of the DDA decreases as (W/L)_n is increased. More specifically, the flicker noise decreases from 175 to 25 and the thermal noise drops from 38 to 8 as (W/L)_n is increased from 9 μm/3 μm to 498 μm/3 μm. A fully differential buffer (FDB) is developed by configuring the DDA in a unity gain feedback configuration as shown in Figure 3.4a, b. DC transfer characteristics of the single-ended buffer and fully differential buffer are as shown in Figure 3.5a and b, respectively. It can be seen that the FDB exhibits a wide input differential range of 2.6 V.

Figure 3.4: Voltage buffer: (a) single ended, (b) fully differential

Figure 3.5: The measured DC characteristics: (a) single ended, (b) fully differential

3.2.4 Highly linear DDA-based filter section

The proposed filter section is based on the fully differential buffer circuit connected in a Sallen–Key lowpass filter configuration. The filter utilises one active element to realise a programmable third-order section. This results in a simple filter section that can be effectively used as a building block for implementing higher-order filters. It simplifies the implementation of various higher-order filters and shortens the design time. The buffer circuit provides class AB low-impedance buffered output for low power consumption and high-speed operation. A fully differential version of the third-order SK lowpass filter is shown in Figure 3.6. The filter characteristics are determined by numerical values of the coefficients in the filter transfer function. SPICE simulations of the entire filter were used to determine the optimum passive component values. The bandwidth of the filter can be varied without changing the quality factor by tuning the resistors together.

Figure 3.6: Fully differential third-order Sallen–Key lowpass filter

Programmability is achieved by using resistor/capacitor arrays and switches to digitally select the appropriate set of components for each standard. Filter bandwidth is programmed to accommodate the GSM, IS-95 and 3G WCDMA standards. Polysilicon resistors are used to achieve high linearity and low signal distortion. This is important in integrated receivers due to the presence of large out-of-band blockers that can result in intermodulation products with frequencies inside the passband of the filter, corrupting the desired signal. This filter section is also useful in achieving non-tuneable highly linear low-noise pre-filters. Such filters are usually used in integrated receivers to attenuate the out-of-band blockers and hence relax the linearity requirements on the following parts of the baseband chain. They are also useful as anti-aliasing filters. The FDB-based filter has the following features:

1. simple structure with one active element per third-order filter section resulting in short design time, low power consumption and good dynamic range;

2. buffered voltage output that simplifies cascading;

3. can be implemented using regular CMOS processes (no floating wells required);

4. class AB operation (low standby power + high current drive capability).

The low-power fully differential filter section was fabricated in a 1.2 μm Nwell CMOS process available through MOSIS. The supply voltages were set to 1.5 V and the total standby current of the filter was 350 μA. The filter is designed to exhibit a bandwidth of about 1.5–2 times the bandwidth of the desired channel. This allows a safety margin to the passband characteristics of the filter against components and temperature variations. Figure 3.7 shows the measured lowpass magnitude responses covering the GSM, IS-95 and WCDMA standards with bandwidths of 100 kHz, 700 kHz and 2 MHz, respectively. The filter section provides a digitally programmable passband that provides a passband ripple of less than 0.2 dB while providing an attenuation of about 70 dB for the blockers. The non-linearity of the filter is measured by the thirdorder intermodulation distortion. Two sinusoidal signals were applied to the input and the output third-order intermodulation was measured for different input amplitudes. Figure 3.8 shows a typical signal spectrum of the third-order intermodulation distortion. The wide range highly linear performance of the filter section is evident from this figure, as the intermodulation components are more than 66 dB below the blocker signal level. It is also worth mentioning that this is achieved without any attenuation of the two blocking signals since they were placed in the pass band of the filter section.

Figure 3.7: AC response of SK third-order filter

Figure 3.8: In-band IM3 of SK third-order filter

3.2.5 Tuneable filter section

The filter section shown in Figure 3.6 offers no frequency tuning. The DDA-based filter of Figure 3.6 can be modified to build MOS-C tuneable filters. This can be accomplished by placing MOS transistors in parallel with the resistors used in realising the fully differential Sallen–Key sections as shown in Figure 3.9. The fully differential nature of the filter cancels the even-order harmonics.

Figure 3.9: Fully differential third-order DDA MOS-C Sallen–Key filter

The filter can be tuned by changing the gate voltage of the triode region MOS resistors. Although the even-order harmonics will be cancelled by the fully balanced nature of the circuit, odd harmonics are still present. While this filter is not suitable for rejecting large out-of-band signals, it is still useful when used after a highly linear pre-filter that attenuates the out-of-band blockers. The proposed filter sections are attractive because they are simple to design and employ relatively few active elements. The high-bandwidth class AB nature of the FDB makes the filter suitable for handling high-bandwidth signals with low power consumption. Figure 3.10 shows the frequency response of a sixth-order MOS-C filter.

Figure 3.10: AC response of sixth-order DDA MOS-C filter

3.2.6 Variable gain amplifier

The third important element in a reconfigurable baseband chain is the variable gain amplifier (VGA). An important requirement for the VGA circuit is to provide good linearity for a wide range of signal swings. The other important consideration in VGA design is DC offset compensation. As outlined earlier, a small DC offset can be amplified by the VGA to a level that saturates the following stages or may cause the output signal to be clipped. Thus, dynamic compensation of the DC offset is an important part of the AGC loop design. Although a voltage buffer can be used to implement filter sections, it cannot be used directly to provide gain. However, sensing the current of the output terminals of FDB and conveying it to an additional current port using current mirrors extends its use to provide gain [5, 6]. By applying the current sensing approach to the FDB, currents through the two output voltages are copied to two new additional current ports (I_zp, I_zn) as shown in the circuit of Figure 3.11 (current mirrors sense the currents of the voltage ports and copy them to the new current ports).

Figure 3.11: Digitally programmable VGA with DC trimming

Two resistors of fixed values are connected to the input terminal while resistor arrays are connected at the output terminals to program the gain digitally. The input voltage minus the DC offset (V_off ) is converted to a current via R_I. This current is conveyed to the output and converted back to a voltage signal by resistors connected at the output terminals. Therefore, the VGA output voltage can be expressed as:

Thus, the gain is set by the ratio of the resistors, and the output DC offset can be cancelled using the V_off terminal. Note that the current-sensed FDB (CSFDB) is configured in a unity gain feedback topology. Therefore, the bandwidth of the amplifier is constant and a maximum which circumvents the finite gain bandwidth product limitation of the DDA.

Resistor arrays (R_L) are used to digitally program the gain. Figure 3.12 shows the frequency response of the variable gain amplifier. It can be seen that the amplifier exhibits almost constant bandwidth at different gain settings.

Figure 3.12: The measured AC response of the VGA

Input referred flicker noise of the VGA was measured to be 40 nV/ at 1 kHz and the thermal noise was 4 nV/ at the maximum gain setting. At the minimum gain setting, they were 61 nV/ and 16 nV/ , respectively. The third-order intercept point (IIP3) of the VGA at maximum gain setting is shown in Figure 3.13. Table 3.1 summarises the performance of different baseband blocks in terms of linearity and noise performance. Figure 3.14 shows a die photo of the DDA-based filters and VGA. The two filter sections on the left can be used in a tuneable MOS-C mode or a highly linear anti-alias filter (AAF) mode. The two sections on the right are VGAs based on supply sensing.

Table 3.1: Measured performance of the reconfigurable chain blocks

Block	In-band IIP3 (dBm)	Out-band IIP3 (dBm)	Noise nV
Pre-filter
GSM	25.2	41	31
IS-95	24.1	38.4	20
WCDMA	17	25.6	17
Ch. select filter
GSM	11.8	26	50
IS-95	15.6	20.6	30
WCDMA	16.4	13.4	26.5
VGA
Max. gain	25	–	16
Min. gain	17	–	4.1

Figure 3.13: The measured IIP3 of the VGA at the maximum gain setting

Figure 3.14: Die photo of the DDA-based programmable filter and amplifier section