2.6 The change to non-complex signal processing


2.6 The change to non-complex signal processing

A diagram of the revised low-IF receiver architecture that avoids the need for a complex ADC is given in Figure 2.8. The basic idea is that instead of processing both the I and Q components of the low-IF output from the frontend, the Q component is discarded and only the I component is passed to a single, non-complex, ΣΔ modulator. The effect of this is to make the spectrum of the now real IF signal symmetrical about zero, as if the IF were itself zero (see the spectrum at B in Figure 2.8). Hence, the spectrum is naturally aligned with that of the quantisation noise spectrum of the single ΣΔ modulator. It is then relatively easy to make the IF signal complex once again by performing the equivalent of a Hilbert transform in the digital channel filters that follow. The rest of the signal chain is the same as the previous system of Figure 2.4.

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Figure 2.8: Non-complex signal processing in a low-IF receiver architecture

An obvious consequence of processing only the I component of the IF signal is a complete loss of image rejection. Any interferer present in the lower adjacent channel will be folded over about zero frequency and become indistinguishable from the wanted signal. There is also a problem with the lower alternate channel as when this signal becomes folded about zero it falls into what is effectively the adjacent channel on the upper side of the wanted signal. In this position the lower tail of its spectrum falls into the band of the wanted signal and due to its relatively high power level the interference caused can degrade receiver sensitivity. Fortunately, both these problems can be easily overcome by filtering the output of the frontend with a simple polyphase filter. The filter attenuates any interferers present in the lower adjacent and alternate channels to a sufficiently low level that they no longer have any significant effect. Except for some interstage buffers, the polyphase filter is a passive device and therefore consumes little DC power.

Like the original system of Figure 2.4, the system of Figure 2.8 uses no AGC and despite the presence of the polyphase filter the vast majority of the channel selectivity is implemented in the digital domain. The DC offsets from the mixers are removed by AC couplings, whose highpass characteriastics have the same 10 kHz cut-off frequency as used previously. The single ΣΔ modulator address the same dynamic range as before but is now very much easier to design for optimum conversion efficiency and for improved adaptability. As will be shown, the dynamic range can be achieved with a fifth-order ΣΔ modulator whose clock frequency is 26 MHz. The high levels of quantisation noise produced by the modulator outside bandwidth of the wanted signal are heavily attenuated by the subsequent digital filters. This pair of FIR filters also provides the necessary channel filtering as well as reconstructing the Q component to make the IF signal complex once again. Only two FIR blocks are required because of the absence of a Q input. It is also important to note that the blocks decimate by a factor of 96 in one step, lowering the sampling frquency from 26 MHz at the input, to the bit rate of 270.8333 kHz at the output. Decimating in one step improves power efficiency by avoiding the need for digital multiplication. The signal processing then involves only changing the sign of the tap weights prior to summation, in response to changes in the state of the binary input bit stream from the ΣΔ modulator.

Whilst improved adaptability is the main objective behind this non-complex signal processing, there will usually be some advantage to be gained in terms of power consumption over the alternative of a fully-complex architecture. To explain this it is helpful to split the power consumption of the whole ADC function into two parts, namely that associated with only the ΣΔ modulators, P1, and that associated with the decimation filters, P2. Furthermore, to establish a point of reference in this elaboration, the two powers P1 and P2 will be defined as the powers consumed by the two parts of the ADC function in an equivalent zero-IF receiver consuming a total power Pzif. In this scenario it is common for P1 and P2 to be of approximately the same magnitude.

To make the step from a zero-IF to a conventional low-IF configuration, some extra cross-branch circuitry is needed between the loop filters of the two ΣΔ modulators to make the pair complex. There will be a very slight increase in power consumption associated with this but the increase is so small as to be ignored. Given the already large over-sampling ratio, there should be no need to change either the clock speed or the bandwidth of the basic loop filters and hence the change in power consumption in switching from a zero-IF to a low-IF for the pair of ΣΔ modulators should be insignificant. As far as the digital filters are concerned, however, moving to the low-IF configuration will double the number of FIR filters required to provide the complex filtering function and hence for the same clock speed, the power consumption will typically double. This means that the power consumption for the conventional low-IF receiver, Pnzif1, will be approximately 50 per cent greater than for the direct-conversion receiver, i.e.

In moving to the low-IF receiver with non-complex signal processing, there is a need to double both the bandwidth of the loop filter in the ΣΔ modulator and the clock speed in order to maintain the same dynamic range in the band 0–200 kHz. In a practical ΣΔ modulator, the power consumption and the noise output in the band of the wanted signal are dominated by the dimensions of the input stages of the loop filter and have only a weak dependency on the clock speed. If the loop filter is modified by just halving the area of the capacitors and not by any change in the size of the active devices, there should be virtually no change in its power consumption. Hence, in needing only one instead of two modulators, there should be a saving of 50 per cent in the power consumption figure P1. Unfortunately, the same is not true of the power consumption of the digital filters since despite the need for only two FIR filter blocks, doubling the clock speed doubles the number of taps required. This means the value of P2 remains unchanged. If this analysis is valid, it can be concluded, therefore, that the power consumption of the ADC function in the non-complex, low-IF receiver (Pnzif2) will be at least 25 per cent higher than that for the direct-conversion receiver but it could be of the order of 17 per cent lower than that of the fully complex low-IF receiver, i.e.

This power saving should be worthwhile but remains to be fully verified in practice.

2.6.1 Polyphase image-rejection filter

Passive polyphase filters were studied some time ago by Gingell [8] and as a prototype structure take the form shown in Figure 2.9. They are a cascade of RC sections each one of which is capable of creating a transmission zero at a frequency, ωzi, such that ωzi =1/RiCi. Whether the zero is at a positive or negative frequency will depend upon the relative polarities of the I and Q components of the input voltage. If each section were to be treated in isolation and driven by a pair of voltage sources, the frequency of the transmission zero would uniquely define the whole of the frequency response and the impedance of the section would be of no consequence. However, because of the loading effect of each successive RC section on its preceding neighbour, the overall frequency response does become affected by the relative impedances and this substantially complicates the synthesis process. As a general rule of thumb, the impedance of the sections should increase in the direction of the output to minimise the loading effects but it is usually necessary to adjust the impedances in a process of trial and error to achieve the most desirable frequency response. Hence, the design procedure involves choosing the transmission zeros to give the desired stop band response and the impedance levels to give the desired passband response. The desired passband response is one which is as flat as possible at positive frequencies close to zero in the region of the wanted signal.

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Figure 2.9: Passive polyphase filter prototype network

Without the polyphase filter, the modified receiver would have no rejection in the lower adjacent channel and therefore the polyphase filter must provide all of the 18 dB required over the band 200 kHz to zero. If the problem with the lower alternate channel is to be avoided it must also provide at least 32 dB of attenuation in the band 400 kHz to 200 kHz. This brings any interferer in the alternate channel at a relative level of +41 dB with respect to the wanted signal down to the maximum permitted level of an adjacent-channel interferer at +9 dB (Figure 2.6). The remainder of the receiver selectivity can then be provided by the digital channel filters. For the purposes of designing the polyphase filter, the attenuation requirement is assumed to be at least 32 dB across both the lower adjacent and alternate channels as this carries no practical penalties and gives some useful performance margin.

To obtain the required attenuation over the approximate band 400 kHz to zero, the transmission zeros for the prototype network of Figure 2.9 are set at the frequencies 80 kHz, 173 kHz and 375 kHz whilst the corresponding resistor values are 1 kΩ, 2kΩ and 4 kΩ. On analysis with a circuit simulator, the network produces a frequency response of the form plotted in Figure 2.10 in which the stopband requirement is largely fulfilled over the band 400 kHz to 60 kHz. The response in the passband at positive frequencies between about 30 kHz and 1 MHz is also flat as required, the slight positive gain (4 dB) being a consequence of the impedance transformations in the filter and the use of ideal voltage sources. Difficulties with physical implementation and with group delay variation prevent the transmission zero at 80 kHz being moved closer to zero but the lack of rejection in this region has no significant impact on the ability of the network to reject an adjacent-channel interferer. In any case, the AC coupling elements elsewhere in the receiver chain will force a transmission zero at DC.

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Figure 2.10: Frequency response of passive polyphase filter

It should be noted that in a practical implementation, the polyphase filter incorporates interstage buffer amplification to help reduce the loading effects of successive stages and to render the thermal noise generated by its resistors insignificant. The power consumption of the buffers is in the region of 10 mW which is a very small fraction of the total power consumption of the RF frontend (typically 135 mW). In the forthcoming system simulations, the filter is modelled as a complex FIR device whose impulse responses are 500 samples in length at a sampling frequency of 26 MHz. This represents a significant computational overhead but is of no relevance to the practical implementation of the filter.

2.6.2 Make-complex channel filter

As previously stated, the output of the single ΣΔ modulator must be made complex once again and this is accomplished with a pair of FIR filters that perform the equivalent of a Hilbert transform [9]. A Hilbert transform of a real function in time I(t) is given by:

where Q(t) has a frequency spectrum whose amplitude components are the same as I(t) but whose phase components are shifted by 90 for positive frequencies and +90 for negative frequencies. In the time domain, it can be interpreted as a convolution of I(t) with the function 1/(πt) whose Fourier transform has a flat amplitude response over all frequencies but a phase response which has a step discontinuity between +90 and 90 at zero frequency. Hence the transform implements an ideal highpass filter whose cut-off frequency is infinitesimally close to zero.

In practice, a close approximation to the transform can be implemented with a pair of filters of the form illustrated in Figure 2.11. Here the FIR filter in the I signal path has a lowpass amplitude response, offering the additional benefit of some high frequency selectivity. The FIR filter in the Q signal path has an identical amplitude response except for the presence of a hole at DC. The width of the hole is determined by the sampling rate and by the length of the impulse responses of the filters. The phase characteristic for the I component is preferably linear and has a slope determined by the delay of the filter. The phase characteristic of the Q component is identical except for the step discontinuity in the middle. Both filters must have the same delay.

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Figure 2.11: Digital make-complex and channel filter arrangement

Whilst a suitable complex filter function can be derived by separate treatment of the two FIR components, the frequency response plotted in Figure 2.12 was obtained by a slightly more direct route whereby a real, lowpass response was first synthesised with an appropriate shape and then simply translated in frequency by +100 kHz. It is then possible to calculate the two respective impulse responses for the I and Q components (Figure 2.13) using an inverse, discrete Fourier transform. The delay of the filter is 18.2 μs, which is equivalent to 475 samples at a sampling frequency of 26 MHz. As shown in Figure 2.12, the filter is substantially more selective than the attenuation template would suggest is necessary but the extra selectivity and deep stopband floor are essential to attenuate the high levels of quantisation noise generated by the ΣΔ modulator.

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Figure 2.12: Frequency response of digital filter

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Figure 2.13: Impulse responses of digital filter

2.6.3 ΣΔ modulator ADC

ΣΔ modulators and their use as ADCs are discussed in some detail in References 10 and 11. As explained, they offer high conversion efficiency, excellent linearity and strong immunity to aliasing due to their high over-sampling ratio. Their basic principle of operation is illustrated by the diagram given in Figure 2.14. There are three main parts to the modulator: the loop filter in the forward signal path; the output limiter; and the digital-to-analogue converter (DAC) in the feedback path. Signals entering the modulator are amplified by the loop filter and then quantised into a set of only two output levels (i.e. +1 and 1). The effect of the quantisation is to generate very large quantities of noise. However, by feeding the noisy output signal back into the input via the very simple DAC, the loop filter is able to alter the shape of the frequency spectrum of the noise and move most of its power to a very high frequency away from the vicinity of the wanted signal. It is then the task of the digital filter that follows to remove the quantisation noise and construct a multibit representation of the wanted signal with the required resolution.

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Figure 2.14: Behavioural model of fifth-order sigma-delta modulator

The noise density at any point in the modulator output spectrum is a function of the sampling frequency and the gain of the loop filter. Hence, a high sampling frequency will reduce the noise density by spreading the noise over a wide bandwidth, whilst the high gain of the loop filter at low frequencies will give more effective cancellation and reduce the noise density in the region of the wanted signal. Typically, the loop filter comprises a cascade of integrators with unity-gain frequencies, fugi. If these are realised as time-continuous circuits the need for any anti-alias filters before the modulator can be largely avoided. In the fifth-order example shown in Figure 2.14, the loop filter is of the so-called ‘feedforward’ type in which the outputs from all five integrators are suitably weighted by coefficients, Ci, before being added together at the common output. Two pairs of integrators are surrounded by feedback elements, B3 and B5 which generate conjugate pairs of transmission poles at 130 kHz and 210 kHz. The remaining integrator without feedback produces a single transmission pole at DC. Offsetting the poles in this way gives the loop filter a greater average gain over a 200 kHz bandwidth, leading to more effective noise shaping and a correspondingly lower level of in-band quantisation noise. Each integrator output passes through a clipping circuit that limits the output swing to a level of Li. Their purpose is to help maintain loop stability under large-signal drive conditions by progressively reducing the effective loop gain. They also prevent the loop from entering a latch-up condition.

With suitable values for the set of parameters fugi, Ci, B3, B5 and the DAC gain, the fifth-order modulator produces an output spectrum of the form shown in Figure 2.15 when its input is a pure tone of 100 kHz. In this case the tone is at the maximum permissible drive level for the modulator, which corresponds to a relative amplitude of 0.7 or a relative power level of 6 dBm. Any higher than this and the modulator becomes unstable. The clock speed is 26 MHz. As shown in the figure, the tone is clearly present on both sides of the spectrum, as is to be expected with only the I component of the IF signal represented. The spectrum of the quantisation noise is also symmetrical about zero, the hole in the centre having a width of approximately 400 kHz. Figure 2.15 also shows the spectrum of the modulator output after it has passed through the pair of digital channel filters. Not only has the pair of filters eliminated the majority of the quantisation noise but it has also made the signal complex once more, as evidenced by the different levels of the tones now seen on either side of the spectrum. The tone on the right at +100 kHz is unchanged in magnitude but that on the left at 100 kHz has been attenuated by approximately 70 dB. This is the effective image rejection ratio of the make-complex filter function. By selective integration of the power in the spectrum, the dynamic range of the modulator and filter combination is found to be in the region of 100 dB.

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Figure 2.15: Output spectra from fifth-order sigma-delta modulator and digital filters




Wireless Communication Circuits and Systems
Wireless Communications Circuits and Systems (IEE Circuits, Devices and Systems Series 16)
ISBN: 0852964439
EAN: 2147483647
Year: 2004
Pages: 100
Authors: Yichuang Sun

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