to the L2 cache. Each of the non-blocking L1 caches are 16KBytes with a unified non-blocking L2 cache of 512KBytes, 1 MByte or 2MBytes. One floating point operation may be retired per clock cycle. It is to be expected that clock rates at and beyond 500 MHz will be realized in the near future and that dual processor systems will be available at reasonable cost providing systems of 1 Gflops peak performance.
3.2.2 DEC Alpha
The DEC Alpha21164 and 21164PC microprocessors retain the performance lead in floating point operation. The 0.35 micron fabrication technology devices operate at a clock rate of up to 533 MHz and are capable of issuing four operations per cycle, two of which may be floating point. This gives the Alpha an unprecedented peak performance of over 1 Gflops. It was this capability that led Cray Research Inc. to adopt the DEC Alpha as the processing core of its T3D and T3E Massively Parallel Processors.
The Alpha uses a Reduced Instruction Set Computer (RISC) architecture distinguishing it from Intel's Pentium processors. RISC designs, which have dominated the workstation market of the last decade, eschew complex instructions and addressing modes, resulting in simpler processors running at higher clock rates, but executing somewhat more instructions to complete the same task. As a result, the Alpha is significantly smaller than the 7+ million transistor Pentium II. The 21164PC has separate 8 KByte L1 caches for data and instructions. The L2 cache is on the motherboard, the AlphaPC 164SX. The 21164 processor is compatible with the AlphaPC 164LX motherboard and includes a larger L1 data cache of 16 KBytes and a unified, 3-way set associative L2 cache of 96 KBytes. The Alpha. unlike the Pentium II, is a true 64 bit architecture.
3.2.3 AMD K6
AMD has provided cost effective and performance competitive microprocessors that are binary compatible with the x86 instruction set. Designed for a 100 MHz system bus using the Super 7 socket, it includes unique instructions for 3D graphics computing.
3.2.4 Future Processors
The next two years will be very interesting for Beowulf-class systems as new microprocessors with very high performance become available. Clock rates climbing to 1 GHz and instruction level parallelism increasing the number of execution units
