Chapter 12. Hardware Address Translation

The hardware address translation (HAT) layer controls the hardware that manages mapping of virtual memory to physical memory. The HAT layer interfaces implement the creation and destruction of mappings between virtual and physical memory and probe and control the MMU. The HAT layer also implements all the low-level trap handlers to manage page faults and memory exceptions. Figure 12.1 shows the logical demarcation between elements of the HAT layer.

Figure 12.1. Role of the HAT Layer in Virtual-to-Physical Translation