Hardware Characteristics of Catalyst LAN Switches

In the Catalyst series switches, we'll look specifically at the 5513 and 5509 chasses and the dependencies between the line cards and the different buses located on the backplane because this backplane architecture varies, depending on slot position. All other switch platforms have constant bus speeds across all slot positions, either 1.2 Gbps (5x00 series), 24 Gbps (4000 series), or 32 Gbps (6000 series).

The 5500 has three buses (classified as A, B, and C) of 1.2 Gbps each, and 13 slots. Figure 10-1 shows the bus and slot designations for a 5513 switch.

Figure 10-1. 5513 Chassis Bus Designation

The slots are designated as follows:

• Slot 1 is reserved for the supervisor engine, which provides switching, local and remote management, and multiple uplink interfaces.

• Slot 2 can contain a redundant supervisor engine, which provides a backup function in case the first module fails. A failure of the active supervisor engine is detected by the standby module, which takes control of supervisor engine-switching functions. If a redundant supervisor engine is not required, slot 2 is available for any switching module.

• Slots 3 through 12 are available for any combination of switching modules.

  Note

  High-speed line cards such as the gigabit Ethernet cards can go only in slots 2 through 5 due to the backplane connection required into all three of the buses.

  
  

• Slot 13 is a dedicated slot, which accepts only the ATM switch processor (ASP) module or the Catalyst 8510 CSR (campus switch router) switch route processor (SRP). When using the ASP in slot 13, the Catalyst 5500 switch accepts LightStream 1010 ATM port adapters in slots 9 through 12. When using the Catalyst 8510 CSR SRP in slot 13, the Catalyst 5500 switch accepts Catalyst 8510 CSR modules in slots 9 through 12.

The Catalyst series switches allocate 192 KB of packet buffers to each port on the switch. This is equivalent to the hardware buffers on the router, yet are static in nature. Due to the switching architecture of the Catalyst, dynamic assignments of hardware buffers are irrelevant. This 192 KB resides on the individual line cards and is not controlled or given out by the supervisor card's memory or DRAM. The supervisor's DRAM has nothing active to do with data packets flowing through the switch, except to initially populate the CAM table with the first instance of a frame.