Conventions Used in This Book

Companion Code

This book is accompanied by downloadable code available from www.wordware.com/files/8086 and www.leiterman.com/books.html. Each chapter with related sample code will have a table similar to the following:

Workbench Files: \Bench\ x86 \chap02\ project \ platform

                         project

platform    

Ram Test

\ ramtest \

\vc6

ram

\ram\

\vc.net

Substituting the data elements in a column into the "Workbench Files:" path will establish a path as to where a related project is stored.

The idea of the code is to be a usable sample of assembly code that has been split open to display its internals for observation and learning. Each module has its own initialization routine to set up function prototype pointers. These are used to vector to the appropriate function designed to be executed by a specific instruction set. This is mainly for the PC as the Xbox only uses a single PIII processor. The correct functions best suited for that processor are assigned to the pointers. If you are one of those (unusual) people running two or more processors in a multiprocessor computer, and they are not identical, then I am sorry! A few motherboards still support this scenario. The good news is that the samples are single threaded so you should theoretically be okay.

One other item: There are many flavors of processors and although the basis of each function call was a cut-and-paste from other functions,the core functionality of the function was not. So there may be some debris where certain comments are not exactly correct; forgive me. There is a lot of code to have to wade through and keep in sync with the different models of 80x86 processors. It has been primarily borrowed from my vector book.

Image Patterning

The images in this book show flow control and sometimes have a split in the middle. These types of images are typically 128-bit SSE, but in cases where the 64-bit MMX has identical functionality, the right side of the split is used to represent the 64-bit sub-set bits 063.

image from book

Sometimes the sub-pattern is not appropriate and so it will be shown separately.

image from book

Some of these instructions support not only 4 single-precision floating-point (SSE) and 2 single-precision floating-point (MMX), but also 2 double-precision floating-point (SSE2). It just so happens that the patterns for MMX and SSE2 match. So refer to the MMX pattern when working with double-precision floating-point.

Processor Legend

Each mnemonic will indicate a version of processor that supports it.

 

Intel

P

Pentium

PII

Pentium II (MMX)

SSE

SSE (Katmai NI)

SSE2

SSE2

SSE3

SSE3 (Prescott NI)

E64T

64-bit Memory

 

AMD

K6

K6

3D!

3DNow!

3Mx+

3DNow! and MMX Ext.

A64

AMD64

Mnemonic

P

PII

K6

3D!

3Mx+

SSE

SSE2

A64

SSE3

E64T

INC



32.64-Bit 80X86 Assembly Language Architecture
32/64-Bit 80x86 Assembly Language Architecture
ISBN: 1598220020
EAN: 2147483647
Year: 2003
Pages: 191

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