Chapter 4. Itanium Instruction Formats and Addressing

The designers of any new computer architecture face many decisions. Their general approaches and their choices of details affect not only the potential success of the first implementation, but also the evolutionary possibilities for all future models. The successes and shortcomings of earlier architectures from all manufacturers provide lessons that design teams dare not forget, as influential critics will inevitably draw such comparisons. Research on new architectural principles may also provide novel and worthwhile ideas for new implementations over the life span of an architecture.

The Itanium architecture and its Explicitly Parallel Instruction Computing (EPIC) principles set a new direction for the industry while it assimilates and emphasizes much of what was good in earlier RISC designs. We continue in this chapter to mention highlights of other architectures where relevant.

How do designers decide upon the width (in bits) for instructions? Will all instructions have the same width (which leads to simplicity of design), or will several classes of instructions with different widths be included in the architecture (which may drive up the cost of implementation)? Will programmers and compiler writers actually use all of the instructions that an architecture implements? Are some instruction types perceived to be essential, while others would be only marginally useful?

The PDP-11 minicomputer architecture, whose implementations delivered a substantial fraction of then-contemporary mainframe performance at a minor fraction of the cost, reflects a mixed strategy: The instruction proper (opcode and all register references) occupies 16 bits, but certain addressing modes involve either one or two additional 16-bit words used as address offsets. Those choices result in seven opcodes for two-address instructions, a much larger number for one-address instructions, and ample provision for zero-address instructions.

Design work on the 32-bit VAX architecture began before semiconductor memory offered increased capacity at declining costs. Compact but variable-length instructions, averaging about 4 bytes, and efficient data storage using numerous sizes of information units (1, 2, 4 bytes) were therefore chosen. Because one byte is used for the opcode, with register references appearing in subsequent bytes, the 32-bit VAX architecture provides many more multiple-operand instructions than its 16-bit predecessor. Some of those are so complex and specialized that they were seldom used.

The principal family of processors from Intel Corporation, with 8-, 16-, and 32-bit datapaths, came into prominence during the market lifetime of the PDP-11 and VAX lines. The Intel architectures differ from the Digital architectures in having relatively fewer processor registers that are not as "symmetric" with respect to the instruction set architecture. As in the VAX and for similar historical reasons, instructions in the Intel designs are variable-length, numerous, and highly differentiated.

Much had changed by the time of the design of the Alpha architecture. The cost of memory was no longer a design constraint. The research community had seriously challenged the hegemony of Complex Instruction Set Computers (CISC), exemplified by the VAX and the Intel 80x86 series. Several manufacturers (Hewlett-Packard, IBM, MIPS^®, and Sun^®) were already having success with Reduced Instruction Set Computers (RISC), which are high-performance scientific workstations and servers incorporating 32-bit datapaths and uniformly sized 32-bit instruction formats.

The Alpha was the first commercially successful architecture with a 64-bit datapath. Several other major manufacturers soon followed with datapath expansion to 64 bits. Since the RISC idea advocates fewer opcodes and dramatically fewer addressing modes than for CISC designs, RISC architecture does not need 64 bits for instruction encoding. RISC designs have thus generally used 32 bits to express each instruction.

In this chapter, we outline the structure of Itanium instructions, ways to access stored data, and the rationale for wider (41-bit) instructions in EPIC design. We also begin to discuss the design, operation, and applications of Itanium instructions, one group at a time. Later chapters take up additional groups of instructions.