13.5 IA -32 Instruction Set Mode

The Itanium architectural specification incorporates a compatibility mode for the IA-32 instruction set architecture, as extended for the Pentium III processor. This included capability is intended to reassure the existing customer base that there is ample opportunity to migrate applications from 32-bit CISC to 64-bit EPIC systems, following well-known precedents in the industry for making previous major architectural transitions (e.g., PDP-11 to VAX, or System/36 and System/38 to AS/400) be as smooth as possible.

The IA-32 capability is an architectural requirement that can be realized in hardware or entirely in software. The Itanium and Itanium 2 processors contain a dedicated unit to decode and expand complex IA-32 instructions into simpler operations that can be carried out as special cases in the standard Itanium execution units. This strategy resembles the way in which later Pentium processor implementations themselves break many of the complex IA-32 CISC instructions into simpler operations that are passed to a RISC-like core in the CPU for execution.

With the IA-32 capability, an Itanium computer can run 32-bit operating systems. More importantly, 64-bit operating systems on Itanium-based computers can launch and run either 32-bit applications or native 64-bit applications. (According to information from Hewlett-Packard Company, an Itanium 2 processor in IA-32 mode offers a performance level comparable to a 300-MHz Pentium Pro.)

In theory, an Itanium computer running a 64-bit operating system could support mixed-mode applications where a single program contains sections of IA-32 instructions and native 64-bit Itanium instructions. Mosberger and Eranian explain why Linux does not support such mixed-mode programming.

Switching between the two instruction sets seems simple enough at an overview level. The Itanium instruction br.ia b2 moves the value in branch register b2 into the instruction pointer and puts the processor into the IA-32 instruction set mode. The processor will then fetch, decode, and execute IA-32 CISC instructions. If any exceptions occur, they are handled by 64-bit code, which then resumes the IA-32 instruction stream if possible. The special decoding unit for IA-32 instructions recognizes a new IA-32 opcode for a JMPE dest instruction that causes the machine state to resume execution of native Itanium instructions beginning at a new destination address, dest.

In detail, however, switching between the two execution modes is far from simple. Before executing the br.ia instruction, the native environment must populate required register contents in order to establish a valid IA-32 machine state. Then IA-32 memory segmentation rules are in effect, virtual addressing is confined to 4 GiB, and all memory references are forced to be little-endian. Furthermore, no instructions can gain access to any Itanium-specific features.

Nearly all of the standard Itanium registers are used by the microarchitecture when operating in the IA-32 instruction set mode. Relatively few registers are preserved, including Br₀ Br₅, Fr₂ Fr₅, and Gr₄ Gr₇. The predicate registers and a few of the application registers will be left in an undefined state. The IA-32 instruction set mode maps an IA-32 machine state and registers onto specific Itanium registers; most remaining Itanium registers, including the register stack region, are used as scratch space by the decoder when it expands the IA-32 instruction stream into the RISC-like micro-operations for the execution units.