State register instructions

As we saw earlier in Appendix A on the SPARC processor, there are several special registers. To read and write to those registers, we use the following instructions.

Table B-18. State register instructions

Opcode	Instruction Syntax	Operation
RDY	rd %y, dreg	Read contents of %y and place into a register
RDASR	rd asr_reg, dreg	Read an ancillary state register into dreg
RDPSR	rd %psr, dreg	Read contents of %psr into dreg
RDWIM	rd %wim, dreg	Read contents of %wim into dreg
RDTBR	rd %tbr, dreg	Read contents of %tbr into dreg
WRY	wr sreg, reg_or_imm , %y	xor the values of sreg and reg_or_imm and write result into %y
WRASR	wr sreg, reg_or_imm, asr_reg	xor the values of sreg and reg_or_imm and write result into an ancillary state register
WRPSR	wr sreg, reg_or_imm , %psr	xor the values of sreg and reg_or_imm and write result into %psr
WRWIM	wr sreg, reg_or_imm , %wim	xor the values of sreg and reg_or_imm and write result into %wim
WRTBR	wr sreg, reg_or_imm , %tbr	xor the values of sreg and reg_or_imm and write result into %tbr

The write instructions are delayed-write instructions. This means that the changes to the register may not be completed until up to three instructions later! When you encounter write instructions while looking at your running kernel or a system crash dump, you will note that they are usually followed by three nop instructions. This programming practice guarantees that the new value has been written to the specified register before the program moves on to the next task.

All but the instructions that address register %y are privileged and therefore are capable of generating privileged instruction traps. Also, these instructions can generate illegal instruction traps under certain conditions.

Miscellaneous state register instructions

The other three SPARC instructions in the state register category are:

Table B-19. Miscellaneous SPARC instructions

Instruction Syntax	Operation
unimp	Unimplemented
stbar	Store barrier
flush address	Flush

The unimp instruction is an unimplemented instruction that, when executed, will generate an illegal instruction trap.

The stbar instruction forces all pending stores and atomic load-stores to complete prior to moving on to subsequent stores and atomic load-stores. The stbar instruction does not generate any traps.

The flush instruction forces all pending memory access instructions involving the specified address to complete before subsequent accesses are attempted.

The stbar and flush instructions are made available for memory management implementations that use memory caches, thus not guaranteeing instant modification of memory.