| Figure 12-1 shows an example of a typical multiprocessor system. Figure 12-1. A Typical Multiprocessor System 
Note that while the processors share the system memory and I/O, each has its own cache and TLB. In order to get the necessary speed benefits from the cache, the cache has to be physically close to the CPU. But this brings up another challenge: how do you maintain consistency between the caches on the various processors? For example, say processor A and processor B both have the same memory address cached in their respective data caches. If processor A modifies the data at that address, it will change the copy in its cache and mark the cache as dirty, but it will not necessarily write that data to main memory immediately. The data that processor B has in its cache is now no longer valid. We get around this problem with a cache coherency check transaction. Every time a processor modifies data that is in its cache, it sends out a cache coherency check transaction. All other processors must check their caches to see if they have copies of the data in their own caches. If a processor has the data in cache and it has been modified, then the data is immediately flushed to main memory. Then that cache line is marked invalid so that the next time the data is needed, it must be read from memory again. To use our example from above, when processor A wants to modify the data, it first sends out the cache coherency check transaction. Processor B sees this transaction and finds that it has that address in its own cache. If the cache line in processor B's cache is dirty, meaning that it needs to be written to memory, processor B immediately flushes that cache line out to memory. It then marks the cache line as invalid so that if it needs the data again later, it will have to load it from memory. If processor B has the data in cache but has not modified it (it is "clean"), then it just has to invalidate the cache line. |
