Buses and Windows 2000
 [oR]A bus is a collection of data, address, and control signal lines that allow devices to communicate. Some buses are wide, allowing simultaneous transmission of many bits of data and control. Others are nothing more than a single wire, allowing devices to transmit data and control in a serial fashion. Some buses allow any device to communicate with any other device on the bus. Others require the presence of a master controller (e.g., a CPU or I/O controller) that is the sole recipient or sender of data. Buses gain and lose popularity over time. Trade-offs between speed, cost, extensibility, and ease of use change as bus technology advances. Device requirements change as new technologies are introduced into the PC world. For example, the common use of digital video on home PCs has produced a need for a simple, ultra-high speed bus. The device driver architecture of Windows 2000 supports new buses easily and efficiently. Many popular buses are supported "out of the box." The remainder of this section describes the currently supported buses on Windows 2000. The descriptions are meant to provide an overview of the bus technology. For more detailed information, please refer to the bibliography. ISA: The Industry Standard ArchitectureThis is the bus that IBM specified for the PC/AT in the early 1980s. It supports 8-bit and 16-bit devices. Because its origins are two decades old, ISA is neither fast nor simple. The bus clock rate is 8.33 MHz. Since even 16-bit transfers take at least two clock cycles, the maximum transfer rate is only about 8 MB/second. Since current CPU speeds are two orders of magnitude faster, ISA is no longer a relevant bus. Its inclusion in Windows 2000 and this book are for backward compatibility reasons only. REGISTER ACCESSISA is the bus by which the need for autorecognition and autoconfiguration were defined. That is, ISA provides the definition for bus chaos. No standards exist for register usage, so devices may grab any I/O address. Generally, I/O addresses between 0x0000 and 0x00FF belong only to devices on the mainboard. Territory between 0x0100 and 0x03FF is available for plug-in cards. Each card is typically assigned a 32-byte contiguous range of register addresses. Sadly, many legacy ISA cards do not decode all 16 I/O address lines. Instead, they decode only the first 10 bits of address. Such cards respond to alias addresses in multiples of 0x400. A device at address 0x300 also responds at address 0x700. When such devices are present in a system, the 64 KB I/O address range diminishes quickly. INTERRUPT MECHANISMSInterrupts on an ISA bus are traditionally handled with two Intel 8259A programmable interrupt controller (PIC) chips (or an emulation thereof.) Each PIC provides eight levels of interrupt priority which, in essence, multiplex eight lines into one. One of the eight input lines (line 2, to be precise) from the first (master) chip routes to the output of the other (slave) PIC, which cascades the sixteen inputs from both chips into a single output. Of course, since one input is lost to the cascade configuration, only 15 lines are left for devices to utilize. Table 2.4 lists the ISA priority levels and their typical assignments. The 8259A chip can be programmed to respond to either edge-triggered or level-sensitive interrupts. This choice must be made for the entire chip, not on a line-by-line basis. Traditional BIOS code initializes both PICs to use edge-triggered interrupts. Therefore, on typical systems, ISA cards may not share IRQ lines. Some main boards that perform custom emulation of the 8259A do allow IRQ-by-IRQ programming for edge vs. level triggering. DMA CAPABILITIESThe standard implementation of ISA DMA uses a pair of Intel 8237 DMAC chips (or an emulation thereof). Each of these chips provides four independent DMA channels. As with the PICs, the standard configuration cascades the two chips, routing the output of the master DMAC through the first channel of the slave DMAC. As before, the cascading technique results in the loss of one channel, leaving seven free for DMA devices. Table 2.5 describes the channel configurations for the two DMACs. When more than one DMA channel is in simultaneous use, the DMAC chips follow a software-selected scheme for prioritization. Typically, highest priority is given to channel 0 and lowest to channel 7. Also note that only the slave DMAC can be used to transfer words (16 bits). These upper channels can transfer data at twice the rate of the lower channels, since they move two bytes per cycle.
Finally, the ISA bus has only 24 address lines. This restricts DMA transfers to only the first 16 MB of system memory. This artifact leaves Windows 2000 with a special problem when dealing with ISA DMA transfers, and chapter 12 discusses the resolution to this complication.
AUTOMATIC RECOGNITION AND CONFIGURATIONAs already mentioned, ISA is the poster child for highlighting the need for dynamic configuration of devices. ISA devices don't announce themselves, they don't provide a resource requirements list, and they are not required to provide software dynamic configuration. Configuration is manual and typically performed with jumpers or DIP switches. Newer ISA devices attempt to correct this problem by conforming to a Plug and Play extension to the ISA standard. These devices gained considerable popularity with the introduction of the Windows 95 operating system. Versions of NT prior to Windows 2000 did not really support Plug and Play, so these devices relied on a special installation program to operate properly with NT. Windows 2000, however, correctly supports these newer ISA devices and exploits their capabilities. EISA: The Extended Industry Standard ArchitectureThe EISA bus is an industry standard extension to the original ISA bus architecture. The attempt of EISA was to remove the ISA limitations without causing undue compatibility problems with legacy ISA cards. Of course, this compatibility requirement necessarily limits the architecture in several ways. For example, while the data bus width was widened to 32 bits, the clock rate remains at 8 MHz. The maximum transfer rate is only about 32 MB/sec. Also, since EISA sockets had to accept ISA cards, it was impossible to fix some electrical noise problems caused by the layout of ISA wiring. REGISTER ACCESSThe EISA bus contains up to 15 slots or sockets. Each slot is assigned a fixed range of 4 KB I/O addresses, thus minimizing port resource conflict. Table 2.6 lists the I/O address ranges assigned to each socket. Since ISA presents an aliasing problem (ISA devices respond to addresses in multiples of 0x400), only 256 bytes of register address space is guaranteed to be unique. INTERRUPT MECHANISMSEISA's interrupt capabilities are a superset of the ISA scheme. While EISA interrupt controllers provide the same 15 levels available on the ISA bus (see Table 2.4), each IRQ line can be individually programmed for edge-triggered or level-sensitive operation. This allows both ISA and EISA cards to coexist on the same bus. DMA CAPABILITIESAs with ISA systems, two ganged DMAC's provide seven independent system DMA channels, numbered 0 through 7. (Channel 4 remains unavailable as it is the tie point for the two devices.)
The EISA architecture extends the ISA DMA model in several ways. First, any of the seven channels can perform 8-bit, 16-bit, or 32-bit data transfers. Thus, any device can use any channel. EISA DMA channels can also be individually programmed to use a variety of different bus cycle formats. This permits new devices to run faster while still maintaining compatibility with legacy ISA cards. Table 2.7 describes the EISA DMA bus cycles.
Another enhancement is the EISA DMAC's 24-bit count register. For 8-bit, 16-bit, and 32-bit devices, this register counts bytes, thus allowing a single transfer operation to move up to 16 MB. For compatibility, the DMAC can be programmed to use this as a word counter for 16-bit transfers. Finally, since EISA DMAC's generate full 32-bit addresses, they can access the entire 4 GB physical address space of the system. There is no restriction placed on DMA transfers occurring in the first 16 MB range as there is with ISA. DEVICE MEMORYThe EISA bus has 32 address lines. Device-dedicated memory can live anywhere within the system's 4 GB address range. This also applies to any onboard ROM the device might have. AUTO RECOGNITION AND CONFIGURATIONSeveral components take part in the EISA configuration process. First, each card is required to implement a 4-byte ID register at location 0xn C80, where n is the EISA slot number from 1 to 0xA. This register identifies the manufacturer, the device type, and the revision level of the card placed in that slot. Second, designers can use the remaining 124 bytes (from 0xn C84 to 0xn CFF) to implement other registers that configure the card. For example, there might be a configuration register for the DMA channel number the card should use, and another for setting its IRQ level. Storing values into these registers is the equivalent of setting DIP switches and jumpers on legacy ISA cards. The third component is a script file that contains the card's resource list and defines the location and usage of any device-specific configuration registers on the card. This file is written in a standard EISA scripting language, and its name is based on the contents of the card's ID register. This script usually comes on a floppy disk supplied by the card's manufacturer. The final piece of the puzzle is an EISA configuration program that runs when a system boots. The program scans the EISA slots, looking for cards in previously empty locations. If it finds one, it uses the contents of the slot's ID register to construct the name of a configuration script and then asks the user for the floppy containing that script. Once the disk is inserted, the configuration program assigns resources to the card. It also copies these assignments to nonvolatile CMOS memory associated with the slot, so it won't be necessary to ask for the script file with each boot. Windows 2000 auto-detects many kinds of EISA cards. To gain access to EISA slots directly, the HAL provides HalGetBusData and HalSetBusData. PCI: The Peripheral Component InterconnectFast networks, full-motion video, and 24-bit pixel displays all require extremely high data transfer rates. The PCI bus is an attempt to satisfy the needs of such demanding hardware. Although the initial design came from Intel, PCI is relatively processor-neutral. PCI has been incorporated into Alpha (DEC) and PowerPC (Motorola) systems. Figure 2.2 shows a typical PCI system. By using a fast bus clock (33 MHz) and a number of clever tricks, the PCI architecture can reach 132 MB/second for sustained 32-bit transfers and twice that rate for 64-bit operations. Some things that contribute to this zippy performance include:
The PCI architecture allows 32 physical units (called devices) to be plugged into one bus. Each of these physical units can contain up to eight separate functional units (called functions). After taking away one function address for generating broadcast messages, there can be up to 255 addressable functions on a single PCI bus. Furthermore, one system Figure 2.2 can have up to 256 separate PCI buses. Figure 2.2. Typical PCI bus system. REGISTER ACCESSAlthough the PCI uses 32-bit addresses, I/O register space on 80x86 machines is still limited to 64 kilobytes, so any PCI registers have to be squeezed into I/O space along with everything else. Furthermore, on systems with an EISA or ISA bridge, designers still need to avoid any I/O addresses being used by legacy hardware. Along with I/O space and memory addresses, PCI defines a range of addresses known as configuration space. The discussion of PCI autoconfiguration explains how configuration space works. INTERRUPT MECHANISMSThe PCI bus has four equal-priority interrupt request lines (INTA-INTD) which are active-low, level-triggered, and shareable. A single-function PCI device has to use INTA, while a multifunction device can use any sequential combination of the four beginning with INTA. The only restriction is that each function can be connected to only one request line. The PCI specification is relatively neutral when it comes to interrupt priorities. Instead, it depends on an external controller to redirect PCI interrupt requests to the proper system interrupt line. For example, on a PC the redirector converts a given PCI function's request on INTA-INTD into a request on one of the IRQ0-IRQ15 lines. To make this work, any PCI function that generates interrupts must implement the following two configuration registers:
This is a very flexible scheme because it doesn't impose any specific interrupt policies on the system designer. This makes it easier to support processor environments other than the 80x86. DMA CAPABILITIESThe PCI specification doesn't include the notion of slave DMA. Instead, the native PCI functions are either bus masters doing their own DMA or they use programmed I/O. The only devices that perform slave DMA on a PCI machine are non-PCI boards plugged into the system's EISA bridge. In a native PCI DMA operation, the participants are referred to as agents, and there are always two of them involved in any transaction.
Because any PCI bus master can be an initiator, it is possible to transfer data directly between two PCI devices with no intermediate stops in memory. This powerful capability lends itself well to high-speed networking and video applications. It's also worth mentioning that the PCI specification doesn't define the policy to be used for arbitrating access to the bus. It only defines the timing of the arbitration signals on the bus. The method used to determine who should go next is system-specific. DEVICE MEMORYDedicated memory used by PCI functions can live anywhere within the 32-bit address space. This feature must be enabled on a function-by-function basis, however, before the PCI device's memory can be seen by the host CPU. An interesting feature of PCI is that a single function can have multiple on-board ROM images, each for a different CPU architecture. This gives vendors the ability to sell the same product in several different markets. The PCI specification defines a standard header format for ROM blocks. Thus, the initialization software can locate the proper chunk of ROM and load it into memory for execution. AUTOCONFIGURATIONThe PCI specification dictates that each individual function on the bus must have its own 256-byte storage area for configuration data. This area is referred to as the PCI function's configuration space. The first 64 bytes of any PCI function's configuration space (called the header) have a predetermined structure, while the remaining 192 bytes belong to the card designer. System software can use the header to identify a PCI function and assign resources to it. The header area includes
At 256 bytes per function, the configuration space for a PCI system could easily grow quite large certainly much larger than the 64 KB I/O space available on x86 processors. Mapping it into memory is always an option, but that too would consume a lot of address space. Instead, PCI functions may access configuration data using the following two registers:
Fortunately, Windows 2000 provides HAL functions to simplify access to configuration data. The HalGetBusData, HalSetBusData, and HalAssignSlotResources functions provide a simple way to access this data. USB: The Universal Serial BusA consortium of companies (including Intel and Microsoft) developed the Universal Serial Bus specification. It was intended to provide a low-cost, medium-speed bus for such areas as digital imaging, PC telephony, and multimedia games. The current USB specification is revision 1.1, and the list of member companies which participate in the consortium continues to grow. A much higher-speed USB proposal is set forth in revision 2.0. Full-speed USB devices transfer data at a rate of 12 Mb/second. Low-speed devices use a slower transfer rate of 1.5 Mb/second. USB version 2.0 should allow data transfer at the rate of 480 Mb/sec. Data is transferred serially over a pair of data wires. Power for some devices is available via separate power and ground wires. Interestingly, USB devices can transfer data at about one-fifth the rate of ISA cards, but without the limitation of needing a mainboard slot. Devices can be connected over a distance of about 5 meters, but USB hubs are also available which extend the range and provide for multiple device connections to a single USB bus. Up to five hubs can be chained together, providing a possible connection distance of almost 30 meters. An example topology of USB devices and hubs is shown in Figure 2.3. Figure 2.3. Example USB topology. REGISTER ACCESSDevice registers are accessed using specific USB commands, 8-bit to 64-bit streams that are used to configure, control power, and retrieve small amounts of device data. Up to 127 USB devices can be connected to a host, with a bus-relative address assigned dynamically as devices are added. The transmission of command data is largely device-specific, so the number and meaning of device commands is defined by each device. Separately, block data is transferred using an isochronous mechanism. Up to 1023 bytes of data can be transferred in a single USB frame. A frame occupies a fixed time interval of 1 millisecond. Command and block data access occurs over a logical abstraction defined by USB as a pipe. The default pipe is used to convey command data, while any number of stream and message pipes can be used to transfer data directly to higher software layers. INTERRUPT MECHANISMSFor USB, true interrupts do not actually exist. Instead, the host USB interface polls devices for interrupt data at fixed intervals, usually every 16 to 32 millisecond. The device is allowed to send up to 64 bytes of data to the host when polled. From a driver's perspective, the interrupt and DMA capabilities of USB are in fact defined by the host adapter that contains the physical USB interface. Considerable effort has been placed on the standardization of the host interface, and two have emerged: the Open Host Controller Interface (OpenHCI) and the Universal Host Controller Interface (UHCI). The host controller provides a conventional interrupt and DMA transfer mechanism. DMA CAPABILITIESUSB devices have no direct access to system memory. They are isolated from system resources by the host USB interface. USB devices do not support DMA. Nevertheless, the USB host interface provides an illusion of DMA for each logical pipe connected to a device. As the host interface collects data from a USB device, it uses DMA to place the received data into system memory. Thus, it is the host interface, not the USB device itself, which provides DMA capability. The bus type to which the host interface connects defines the DMA rules. AUTOMATIC RECOGNITION AND CONFIGURATIONUSB was designed to support Plug and Play directly and intelligently. Each USB device attaching to a USB port or hub signals its presence and reports manufacturer ID and device descriptor. Windows 2000 supports Plug and Play of USB devices by detecting their presence, locating, and then installing the appropriate driver for the device. IEEE 1394: The Firewire TM BusOriginally proposed and implemented by Apple Computers, the Institute of Electrical and Electronic Engineers (IEEE) defined a high-speed, peer-to-peer serial bus to accommodate applications where the lower speed of USB proved inadequate. IEEE 1394 (currently IEEE 1394a-2000) describes a bus standard that supports three transfer rates, 100, 200, and 400 Mb/sec. (IEEE 1394b will support faster rates). Even at the slowest rates, more than 10 MB/sec are transferred, faster than with the original ISA mainboard bus. The name Firewire remains a trademark of Apple Computers. The term 1394 is typically used to describe the bus on PC hardware. Sony and other camcorder companies are using the term "i.LinkTM " for their implementation of 1394. Each 1394 device can connect to its host using a 4.5 meter, 6- or 4-wire cable. Up to sixty-three devices can be daisy-chained over a total distance of 72 meters. Bridges are devices that span buses and thus allow the connection of up to 62 additional devices. Up to 1024 buses may be bridged together. The theoretical number of devices allowed in the 1394 topology is 64 K. A 16-bit Node ID is assigned when a new device is attached. The 6-wire cable includes two twisted pairs for separate data transfer and clocking of data, and one pair for device power. The entire cable is shielded and jacketed and terminates with a Nintendo Gameboy-derived connector. Typical uses for 1394 interfaces are found on digital cameras that must transfer large amounts of data from device memory to a PC. Digital video editing typically requires significant bandwidth, and new equipment with this capability now includes a Firewire interface. REGISTER ACCESSIEEE 1394 conforms to the IEEE 1212 standard of Control and Status Register (CSR) architecture. The CSR standard defines a 64-bit fixed addressing scheme, which includes a 10-bit bus number, a 6-bit Node ID with the remaining 48 bits left for device use. While recommendations for proper usage are given in the 1212 spec, the 256 TB (terabyte) address range for device registers is sufficient for most needs. As with the USB scheme, device register usage is reserved for control and status and limited data transfer (up to 64 bytes). Isochronous clocking is used when bandwidth must be guaranteed (e.g., camera data) while asynchronous clocking is used for guaranteed arrival (e.g., hard disk data). INTERRUPT MECHANISMSAs with USB, 1394 simulates device interrupts. A device must send a packet of data to announce its status or state when host intervention is required. The driver for the device must respond to the data placed in the system address space by the 1394 interface. The 1394 family of standards includes an Open Host Controller Interface. The OHCI specification is the standard of most significance to a driver author. It provides a conventional interrupt and DMA mechanism for 1394 devices. The 1394 Trade Association provides a convenient link to the OHCI spec and other relevant information: http://www.1394.ta.org. DMA CAPABILITIESThe host interface adapter uses DMA to transfer data and commands to and from system memory. The 1394 devices cannot directly access system memory. OHCI adapters provide a range of addresses that are routed by software and the DMAC of the host interface directly into system memory. Thus, an illusion of DMA is provided for each device. AUTOMATIC RECOGNITION AND CONFIGURATIONThe 1394 was designed to support Plug and Play directly and intelligently. Each device that attaches to the bus signals its presence with a bus reset. The host (or other nodes) then enumerates the device's configuration ROM to discover it. The PC Card (PCMCIA) BusAbout ten years ago, several companies jointly developed a standard bus architecture for mobile devices. Initially, the focus was on memory cards and the group became the Personal Computer Memory Card International Association (PCMCIA). The mobile environment is short on size and power resources, so a small form factor was developed with heavy emphasis on power management. Today, more than 300 companies are members of PCMCIA. The original PC Card standard defined a 68-pin interface with one of three card thicknesses, Type I, Type II, and Type III. The standard defined bus speeds comparable to ISA again, the emphasis was on power and size, not performance. The term PCMCIA card is often used interchangeably with PC Card. This terminology creates confusion; PCMCIA is an organization, while PC Card defines a bus interface. Today PCMCIA defines (at least) three bus interfaces: PC Card, DMA, and CardBus. Thus, a PCMCIA card does not signify which kind of card is being discussed. The original PC Card bus clocked at ISA speeds, 8 MHz, and allowed for 8-bit or 16-bit devices. Thus, the maximum transfer rate for a 16-bit card was 16 MB/sec. The CardBus architecture allows for 32-bit devices. It clocks at the PCI bus speed of 33 MHz, thus allowing a maximum transfer rate of more than 128 MB/sec. REGISTER ACCESSThe PC Card standard defines a 26-bit address range for its I/O access (64 MB). Otherwise, addressing is similar to the ISA scheme. For CardBus, a full 32-bit address range is defined, similar to the PCI bus. INTERRUPT MECHANISMSThe PC Card and CardBus standards define a single pin for interrupts, IREQ or CINT. It is level-sensitive and can therefore be shared with other cards on the same bus. However, multifunction PCMCIA cards must arbitrate in software for sharing of the single interrupt wire. DMA CAPABILITIESThe original PC Card standard did not allow for any DMA access. A newer standard released in 1995 added DMA to a PC Card extension, aptly titled just DMA. The DMA standard allows for byte or 16-bit word transfers in a manner similar to ISA. The standard assumes that devices will be bus slaves (of shared DMACs) and, like ISA, bus master DMA cards are difficult to implement. The CardBus standard allows DMA much like the PCI bus. Bus mastering is a straightforward addition to a CardBus device, although the limited form factor requires considerable component integration. Sixteen-bit and 32-bit data transfers are allowed up to the CardBus clock speed of 33 MHz. AUTOMATIC RECOGNITION AND CONFIGURATIONThe intended uses of the PC Card bus mandated that complete Plug and Play capabilities be included. PC Cards continue to set the standard for hot plugability and autoconfiguration. Software for the PC Card or CardBus standards is layered in two major pieces: Socket Services and Card Services. The Socket Service is BIOS-level software that manages one or more sockets on a system. It is responsible for detection and notification of device insertion or removal. The Card Service software layer manages hardware resources for a given card.
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EAN: 2147483647
Pages: 156
- Structures, Processes and Relational Mechanisms for IT Governance
- Integration Strategies and Tactics for Information Technology Governance
- Measuring and Managing E-Business Initiatives Through the Balanced Scorecard
- Governance in IT Outsourcing Partnerships
- Governance Structures for IT in the Health Care Industry