The Hardware Design Process | Embedded LinuxR. Hardware, Software, and Interfacing

The hardware design process can be broken down into eight phases:

Design the external interface hardware.
Find space in the memory map.
Find the CPU configuration register base address.
Configure the memory controller.
Assign the output module enable signal.
Configure the I/O port controller.
Write the helloworldbit testing device driver.
Write the liftmon_snowcon device driver.

Using memory-mapped I/O requires the interface circuit to appear as though it is a static RAM device. The circuit should respond to memory chip selection, write enabling, output enabling, and the bidirectional data bus, and it should perform address decoding. The I/O requirements of six inputs and eight outputs can be implemented by using bytewide data transfers. Upon reset, the interface circuit must not energize any output control module. When the liftmon_snowcon device driver initializes (that is, when the module loads), it should turn off all the output control modules and enable output module driving circuit.

Memory-mapped I/O hardware connects to the CPU bus and acts like static RAM memory. The I/O interface circuit needs to be placed in the memory map where no other memory or device (such as an Ethernet controller) exists. Using manufacturers' documentation, the Project Trailblazer engineers need to find a place in memory to locate the I/O circuit.

The ARM and PowerPC processors configure their internal controllers and peripherals by using special configuration registers that are located at a specific memory address upon reset. Using memory-mapped I/O requires determining the register address base location. With this location and predefined offsets from this memory location, the CPU memory controller and general-purpose I/O port configurations can be modified.

Some board designs and operating systems move the register base location after reset. It's possible to find the register base address either in CPU documentation, in Linux source code, or by making a software system call.

When the I/O circuit is physically mapped to a memory location, the CPU's memory controller needs to be configured. The ARM and PowerPC memory controllers offer interfaces to SRAM, EPROM, Flash EPROM, DRAM, SDRAM, and SRAM-like devices in burst and nonburst modes. The Project Trailblazer engineers need to configure the ARM and PowerPC processors to access the I/O circuit as an SRAM-like device.

The interface circuitdesign requires a signal called OutputModuleEnable to control the output enable for the output control modules. The device driver asserts OutputModuleEnable during initialization. Both the ARM and PowerPC processors have many pins that could serve as this control line. The Project Trailblazer engineers need to determine which unused pin, that's available on an expansion connector, should be used.

Before the Project Trailblazer engineers can access the OutputModuleEnable, the CPU's port I/O controller must be configured. Many I/O pins on both the ARM and PowerPC processors have an alternate function for on-chip peripherals, such as serial port signals. The Project Trailblazer engineers need to configure the I/O controller so that the OutputModuleEnable signal doesn't use an alternate function and so that it is an output.

Configuring CPU registers is easy. It's a good idea to test the configuration with a simple program. The Project Trailblazer engineers need to write a simple device driver to test their ARM and PowerPC CPU configuration. This simple device driver, helloworldbit, should configure the CPU memory and I/O controllers and then access a memory location and toggle the OutputModuleEnable signal. By using a logic probe or oscilloscope, the Project Trailblazer engineers need to verify proper configuration of the CPU registers.

With the hardware design complete and tested, the Project Trailblazer engineers need to write the lift monitoring and snow-making control device driver for the ARM and PowerPC processors. Using the liftmon_snowcon.c device driver source code from Chapter 7, the engineers can develop lift monitoring and snow-making control device drivers for the MediaEngine and the RPX-CLLF.

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