A Cache-based Message Passing Scheme for a Shared-bus Multiprocessor
Website of Bruno R. Preiss
A Cache-based Message Passing Scheme for a Shared-bus Multiprocessor
Bruno Richard Preiss and V. Carl Hamacher. In Proc. 15th Int. Symp. on Computer Architecture , pages 358-364, Honolulu, HA, May 1988. Institute of Electrical and Electronics Engineers, Inc.[48].This paper describes a scheme for using cache-based hardware to provide simple and efficient message passing support for message-based software systems on a tightly-coupled , shared-bus multiprocessor. This approach is based on the utilization of the existing interprocessor communications medium, the shared bus, to effect the exchange of single-word messages. Communication between processes is accomplished over logical channels using simple, blocking send and receive primitives. The physical processor/channel interface is designed so that the message transfer primitives can be implemented as single machine instructions, namely store and fetch . Special-purpose caches, called message caches ,mediate channel operations and effect the exchange of messages over the shared bus.
Copyright 1988 by Institute of Electrical and Electronics Engineers, Inc.
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Copyright 2002 by Bruno R. Preiss, P.Eng. All rights reserved.
Tue Jan 1 13:41:25 EST 2002
Website of Bruno R. Preiss
Data Flow on a Queue Machine
Bruno Richard Preiss and V. Carl Hamacher. In Proc. 12th Int. Symp. on Computer Architecture , pages 342-351, Boston, MA, August 1985. Institute of Electrical and Electronics Engineers, Inc.[47].An execution model that supports program reentrancy, recursion, and automatic run-time loop unravelling is described. This execution model is based on queue machines that execute acyclic data-flow graphs. The use of separate instruction and data token spaces allows program reentrancy. Execution environments called contexts executeacyclic data-flow graphs associated with high-level code blocks. Iteration and function activation are implemented by the dynamic creation of contexts and do not require the use of tagged tokens.A multiprocessor architecture that supports this execution model is proposed. The system architecture is based on a partitioned ring in which each partition of the ring is a conventional processor/memory bus.
The proposed architecture has been simulated in software. A number of test programs have been developed and their execution on the proposed architecture has been evaluated. The performance of the proposed architecture with various
numbers of processing elements is described. In addition, a number of task scheduling algorithms are presented and evaluated.
Copyright 1985 by Institute of Electrical and Electronics Engineers, Inc.
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Copyright 2002 by Bruno R. Preiss, P.Eng. All rights reserved.
Tue Jan 1 13:41:25 EST 2002
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Short-Packet Transfer Performance in Local Area Rings
Wayne Mervin Loucks, V. Carl Hamacher, Bruno Richard Preiss, and Luke Wong. In Proc. INFOCOM `84 , pages 174-184, San Francisco, CA, April 1984. Institute of Electrical and Electronics Engineers, Inc.[18].The performance of various access control protocols for high-speed, bit-serial, computer communication rings is studied. Local Area Computer Network (LACN) applications in which message packets are of fixed length and shorter than the total inherent propagation delay around the ring are the focus of attention. Token, slotted, and static and dynamic insertion rings are included in the study. In all cases, the transmitting station is responsible for removing its transmitted packet from the ring. Under this type of removal rule, it is possible for the stations to execute their access control algorithms with only a short, fixed, inline delay in each station. The insertion rings dynamically switch longer delays (insertion registers) into the ring when they are transmitting a packet. The transmitter-remove rule operates in such a way that hogging of the ring transmission facility by a subset ofstations cannot occur. Expressions that approximate average transfer time as a function of utilization are derived for all ring types and are checked by simulation. For the assumed short-packet environment, it is found that token rings exhibit the slowest transfer times, while dynamic insertion rings arefastest .
Copyright 1984 by Institute of Electrical and Electronics Engineers, Inc.
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Copyright 2002 by Bruno R. Preiss, P.Eng. All rights reserved.
Tue Jan 1 13:41:25 EST 2002