This paper describes a scheme for using cache-based hardware to provide simple and efficient message passing support for message-based software systems on a tightly- coupled , shared-bus multiprocessor. This approach is based on the utilization of the existing interprocessor communications medium, the shared bus, to effect the exchange of single-word messages. Communication between processes is accomplished over logical channels using simple, blocking send and receive primitives. The physical processor/channel interface is designed so that the message transfer primitives can be implemented as single machine instructions, namely store and fetch . Special-purpose caches, called message caches , mediate channel operations and effect the exchange of messages over the shared bus.
Copyright 1988 by Institute of Electrical and Electronics Engineers, Inc.
Full text. BibTeX entry.
Copyright 2002 by Bruno R. Preiss, P.Eng. All rights reserved.
Tue Jan 1 13:41:25 EST 2002