Multi-Threaded Pipelining in a RISC Processor | Data Structures and Algorithms with Object-Oriented Design Patterns in C++

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Ian Donald MacIntyre and Bruno Richard Preiss. In Proc. 1991 Canadian Conf. on Elec. and Comp. Eng. , pages 7.3.1-7.3.6, Qu bec, P.Q., September 1991. Canadian Society for Electrical and Computer Engineering[21].

This paper examines the effects of multithreaded pipelining on the CPI (cycles per instruction) of a RISC processor. The desired CPI in a conventional (single-threaded) RISC processor is one instruction per cycle. However, the CPI is typically more than one because of data hazards, control hazards, and resource hazards in the pipeline.
A multi-threaded processor performs a context switch between every instruction. Multi-threaded pipelining holds out the promise of achieving a lower CPI because it can eliminate data and control hazards, and mask the effects of memory latency. However, multi-threaded pipelining reduces cache hit ratios and requires more chip area to implement.

In this paper, we present a model for predicting the CPI of a multi-threaded pipelined processor. We also present the results of trace-driven simulations of single- and multi-threaded processors. These data show that, for reasonable implementation technologies, and taking into account the chip area penalty, a multi-threaded processor can achieve a lower CPI than a single-threaded processor.

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