5.7 References | From ASICs to SOCs: A Practical Approach

1. J. M. Rabaey and M. Pedram. Low-Power Design Methodologies . Norwell, MA: Kluwer Academic Publishers, 1996.

2. K. Roy and S. C. Prasad. Low-Power CMOS VLSI Circuit Design . New York: Wiley Interscience Publication, 2000.

3. C. Settles and S. Emerson. "Centralized Clock Control Tames Power Consumption in SOCs." Portable Design Magazine , pp. 60 “65, January 2000.

4. C. Piguet. Low-Power DSP Processors . DSP Course, March 1999, Monterey, CA.

5. R. Burch, F. N. Najm, P. Yang, and T. Trick. "A Monte Carlo Approach for Power Estimation." IEEE Transactions on VLSI Systems , pp. 63 “71, March 1993.

6. T. L. Chou and K. Roy. "Accurate Power Estimation of CMOS Sequential Circuits." IEEE Transactions on VLSI Systems , pp. 369 “380, September 1996.

7. F. N. Najm. "A Survey of Power Estimation Techniques in VLSI Circuits." IEEE Transactions on VLSI Systems , pp. 446 “455, December 1994.

8. M. J. Irwin. "Low-Power Design for Systems on a Chip." Department of CSE, Penn State University. www.cse.psu.edu/~mji

9. Synopsys' PowerCompiler. www.synopsys.com/news/press/pc_pr.html

10. J. Frenkil. "Low-Power Design Tools, Where Is the Impact?" Design Automation Conference, June 1997.

11. M. Poncino. "Power Optimization of Memory Processor Interfaces in Embedded Systems." www.eda.sci.univr.it

12. M. A. Cirit. "Estimating Dynamic Power Consumption of CMOS Circuits." IEEE International Conferences on Computer Aided Design , pp. 534 “537, November 9 “12, 1987.

13. R. Burch, F. Najm, P. Yang, and D. Hocevar. "Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits." 25th ACM/IEEE Design Automation Conference , Anaheim, CA, pp. 294 “299, June 12 “15, 1988.

14. F. Najm, R. Burch, P. Yang, and I. Hajj. "CREST ”A Current Estimator for CMOS Circuits." IEEE International Conference on Computer Aided Design , Santa Clara, CA, pp. 204 “207, November 7 “10, 1988.

15. "Managing Power in Ultra Deep Submicron ASIC/IC Design." www.synopsys.com/products/power/low_power_wp.pdf

16. www.xemics.com

17. K. Itoh, K. Sasaki, and Y. Nacagome. IEEE Symposium of Low Power Electronics , pp. 84 “85, October 1994.

18. "Power Analysis Technology Backgrounder," Synopsys Inc. Mountain View, CA, September 1995.

19. C. Deng. "Power Analysis for CMOS/BiCMOS Circuits." In Proceedings of the 1994 International Workshop on Low-Power Design , pp. 3 “8, April 1994.

20. K. Itoh, K. Sasaki, and Y. Nakagome. "Trends in Low-Power RAM Circuit Technologies." Proceedings IEEE , April 1995.

21. H. W. Johnson and M. Graham. High-Speed Digital Design . Upper Saddle River, NJ: Prentice-Hall, 1993.

22. A. Chandrakasan, R. Allmon, A. Stratakos, and R. Brodersen. "Design of Portable Systems." Proceedings CICC Conference , May 1994.

23. A. Chandrakasan, S. Sheng, and R. Brodersen. "Low-Power CMOS Digital Design." IEEE Journal of Solid State Circuit , SC-27, pp. 658 “691, 1992.

24. W. C. Athas. Low-Power Design Methodologies . Norwell, MA: Kluwer Academic Press, 1995.

25. N. H. E. Weste and K. Eshraghian. Principles of CMOS VLSI Design: A System Perspective . Reading, MA: Addison-Wesley Publishing Company, 1994.

26. M. Takada. Low-Power Memory Design . IEDM Short Course Program, 1993.

27. F. Ferguson and A. Mauskar. "High Level Design for Low Power." Proceedings of Electronics Design Automation and Test Conference , August 1995.

28. D. K. Liu and C. Svensson. "Power-Consumption Estimation in CMOS VLSI Chips." IEEE J. Solid State Circuits , vol. 29, pp. 663 “670, 1994.

29. S. R. Powell and P. M. Chau. "Estimating Power Dissipation of VLSI Signal Processing Chips: The PFA Technique." VLSI Process. , vol. 7, pp. 250 “259, 1990.

30. J. Lipman. "EDA Tools Let You Track and Control CMOS Power dissipation." EDN Magazine , November 1995.

31. M. Farrahi, G.E. Tellez, and M. Sarrafzadeh. "Memory Segmentation to Exploit Sleep Mode Operation." Proceedings of the Design Automation Conference , June 1995.

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