Figure 4.12: Multislot power versus time mask for the NB and for the AB (a) power level is higher on first time slot; and (b) power level is higher on second time slot.
Figure 4.13: Circuit for a convolutional code.
Figure 4.14: Circuit for the rate 1/2 code defined by G0 and G1.
Figure 4.15: Example with the input bit sequence 1 0 0 1.
Figure 4.16: Discrete memoryless channel.
Figure 4.17: Example of 1/2 convolutional code.
Figure 4.18: Associated trellis diagram for the example code.
Figure 4.19: Representation of the survivors at step 5.
Figure 4.20: BER estimation for the RXQUAL measurement operations in the (a) transmitter and (b) receiver.
Figure 4.21: IF receiver architecture.
Figure 4.22: Problem of image frequency in IF architecture.
Figure 4.23: Zero-IF receiver architecture.
Figure 4.24: The dc offset sources in the ZIF receiver
Figure 4.25: AM problem.
Figure 4.26: Near-zero-IF architecture.
Figure 4.27: NF calculation.
Figure 4.28: Demodulation performance BLER versus E b /N , static channel. (From [5].)
Figure 4.29: Nonlinear response.
Figure 4.30: IP3 definition.
Figure 4.31: AGC loop mechanism.
Figure 4.32: Synthesizer lock-time constraint for a class 12 MS.
Chapter 5: Radio Interface: RLC/MAC Layer
Figure 5.1: Mapping of PSI messages.
Figure 5.2: Example of mobile allocation definition.
Figure 5.3: Example of the use of CCCH_GROUP and PAGING_GROUP concepts for the required paging subchannel PCH decoding.
Figure 5.4: Downlink signaling failure mechanism.
Figure 5.5: Channel request and packet channel request format.
Figure 5.6: Access persistence control on PRACH.
Figure 5.7: One-phase access establishment scenario on CCCH.
Figure 5.8: Two-phase access establishment scenario on CCCH.
Figure 5.9: One-phase access establishment scenario on PCCCH.
Figure 5.10: Two-phase access establishment scenario on PCCCH.