Chapter 12. Reset & InitializationThe Previous Chapter There are two aspects in dealing with link or internal errors in HyperTransport: detection and handling. The previous chapter described all error types and discussed what devices may do about them. Some devices may chose to detect and handle some errors but not others. The PCI configuration space registers used to program the error strategy and log errors were described, as well as the reporting mechanisms: error response, fatal and non-fatal interrupts, and Sync flood. This Chapter Reset signalling and timing along with actions taken by the system and devices during reset are the primary topics discussed in the chapter. This chapter also discusses the software initiated reset and why it's required. The process of determining the default speed and link width and the subsequent software tuning of bus speed and link width are also detailed. The Next Chapter HyperTransport uses PCI configuration. The next chapter describes HyperTransport configuration for devices other than HyperTransport-to-HyperTransport bridges: host bridges, tunnels, and end (I/O hub) devices. HyperTransport-to-HyperTransport bridges have a different PCI header format than these devices, and are described separately in the chapter on HT Bridges. Many attributes of HyperTransport configuration are exactly the same as for generic PCI devices, although some PCI configuration space header fields are used differently in HyperTransport, and some not at all. Devices require at least one HyperTransport-specific advanced capability register block in addition to the basic PCI configuration space header fields. |