Trodden J., Anderson D. HyperTransport System Architecture / Chapter 12. Reset Initialization

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HyperTransport System Architecture
Authors: Trodden J., Anderson D.
Published year: 2003
Pages: 93-94/182

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Chapter 12. Reset & Initialization

The Previous Chapter

There are two aspects in dealing with link or internal errors in HyperTransport: detection and handling. The previous chapter described all error types and discussed what devices may do about them. Some devices may chose to detect and handle some errors but not others. The PCI configuration space registers used to program the error strategy and log errors were described, as well as the reporting mechanisms: error response, fatal and non-fatal interrupts, and Sync flood.

This Chapter

Reset signalling and timing along with actions taken by the system and devices during reset are the primary topics discussed in the chapter. This chapter also discusses the software initiated reset and why it's required. The process of determining the default speed and link width and the subsequent software tuning of bus speed and link width are also detailed.

The Next Chapter

HyperTransport uses PCI configuration. The next chapter describes HyperTransport configuration for devices other than HyperTransport-to-HyperTransport bridges: host bridges, tunnels, and end (I/O hub) devices. HyperTransport-to-HyperTransport bridges have a different PCI header format than these devices, and are described separately in the chapter on HT Bridges. Many attributes of HyperTransport configuration are exactly the same as for generic PCI devices, although some PCI configuration space header fields are used differently in HyperTransport, and some not at all. Devices require at least one HyperTransport-specific advanced capability register block in addition to the basic PCI configuration space header fields.

General

HyperTransport defines cold reset, warm reset, and a link initialization process. Link initialization involves determining the widest link and highest clock frequency that two devices attached to a link may use. Link initialization involves a multi-step process that is initiated during cold reset.

A hardware-based handshake process determines the link width to be used immediately following cold reset. This process is performed by devices at both ends of every link. The handshake determines the smaller of the devices attached to each link with respect to maximum receiver width (up to 8 bits). For example, one receiver may have a maximum width of 4 and the other a maximum width of 8, thus the smaller CAD width (4) is used. A detailed description of this process is described in the section entitled, "Low-Level Link Width Initialization" on page 282. Also, following cold reset all devices use the default clock frequency of 200 MHz (required by all devices). The initial width negotiated and the default speed may be less than the actual capability of the devices and thus require further tuning.

Next, firmware (e.g. BIOS) optimizes all links so they use the widest path and the fastest clock that the attached devices support. This is done by reading link capability registers within the devices attached to each link. These registers report the maximum link width and maximum frequency at which each device is designed to operate . Software determines the highest common actual CAD width and clock frequency to be used.

Finally, firmware initiates a Warm RESET (or assertion of LDTSTOP#) to cause the new link width and clock values to take effect. Warm RESET or LDTSTOP# assertion is typically triggered by writing to an implementation-specific register in the I/O Controller Hub.

Details regarding the process described above are discussed in the remainder of this chapter. Note however, that portions of the RESET initialization process that involve clock and buffer initialization are detailed in the section called "Link Initialization" on page 282.