List of Figures

   

Figure 1-1 Current Limitations 2

Figure 1-2 Basic Terms 7

Figure 1-3 Point-to-Point Topology 8

Figure 1-4 Two Point-to-Point Connections 8

Figure 1-5 Arbitrated Loop Topology 9

Figure 1-6 Fabric Topology 10

Figure 1-7 Typical Fibre Channel Campus Topology 11

Figure 2-1 Fibre Channel Protocol Functional Levels 14

Figure 2-2 Placement in a Topology 15

Figure 2-3 Functional Levels 16

Figure 2-4 Fibre Channel Framing levels 17

Figure 2-5 FC-0 Connectors 18

Figure 2-6 Fiber Cable Components 20

Figure 2-7 Light Transmission 21

Figure 2-8 Bend Radius 21

Figure 2-9 8B/10B Encoding 24

Figure 2-10 8B/10B Translation 25

Figure 2-11 FC-2 Frame Structure 27

Figure 2-12 Frame Header Structure 28

Figure 2-13 FC-3 Common Services Level 31

Figure 3-1 FC-AL Private Loop 37

Figure 3-2 FC-AL Public Loop 38

Figure 3-3 FC-AL Fabric 39

Figure 3-4 Monitoring or Idle State 43

Figure 3-5 Arbitration Process 44

Figure 3-6 The Opened State 45

Figure 3-7 Open Loop 46

Figure 3-8 Closing the Loop 47

Figure 3-9 Cascaded Shortwave Hub Topology 50

Figure 3-10 Cascaded Long-wave Hub Topology 51

Figure 4-1 Target Address Space Limitations 54

Figure 4-2 LUN Address Space Limitations 55

Figure 4-3 Work-around for Target Address Limitations 56

Figure 4-4 Work-around for LUN Address Limitations 56

Figure 4-5 Addressing Methods 57

Figure 4-6 Hardware Path 58

Figure 4-7 Nibble Conversion of Loop Address on a 30-Slot Array 60

Figure 4-8 Example of LUN using Peripheral Device Addressing 61

Figure 4-9 Hewlett-Packard HA FC Disk Array 61

Figure 4-10 Example of an ioscan 62

Figure 4-11 Example of Logical Unit Addressing 63

Figure 4-12 Example for Converting the MUX Loop Address 64

Figure 4-13 Hardware Path for the MUX Control Port 65

Figure 4-14 Example Hardware Path for a Device on MUX bus 3 65

Figure 4-15 Example MUX ioscan with Attached Devices 66

Figure 4-16 Example of Volume Set Addressing 67

Figure 4-17 Example of Deriving Loop Address using Volume Set Addressing 68

Figure 4-18 Deriving a LUN Hardware Path 69

Figure 4-19 Final Hardware Path for LUN 179 70

Figure 5-1 Hewlett-Packard's Fibre Channel Chips 75

Figure 5-2 TACHYON Internal Block Diagram 78

Figure 5-3 TACHYON Pin-out Block Diagram 80

Figure 5-4 A3404A Fibre Channel Adapter (for K-Class Systems) 82

Figure 5-5 A3636A Fibre Channel Adapter (for T-Class Systems) 83

Figure 5-6 A3591A Fibre Channel Adapter (for D-Class Systems) 84

Figure 5-7 A3740A Fibre Channel Adapter (for V-Class Systems) 85

Figure 5-8 A3724A/A4839A FC-AL Hub 86

Figure 5-9 Cascaded Long-wave Hub Topology 88

Figure 5-10 Cascaded Shortwave FC-AL Hub Configuration 90

Figure 5-11 Incorrect Cabling Example: Connected Ports on the Same Hub 90

Figure 5-12 Incorrect cabling example: more than one cable connection between hubs 91

Figure 5-13 Incorrect cabling example: more than two hubs connected 91

Figure 5-14 A3661A HA FC Disk Array 92

Figure 5-15 Basic Topology, High Availability Version: Host with Two FC I/O Adapters 94

Figure 5-16 Basic Topology, High Availability Version: Host with Four FC I/O Adapters 95

Figure 5-17 Basic Topology, NonHigh Availability Version: Host with Four FC I/O Adapters 96

Figure 5-18 Single-System Distance Topology 98

Figure 5-19 High Availability (redundant loop) Topology 101

Figure 5-20 High Availability, Distance, and Capacity Topology 104

Figure 5-21 Campus Topology 105

Figure 5-22 A3308A SCSI Multiplexer 106

Figure 5-23 FC-SCSI MUX Topology with Two DLT Libraries 107

Figure 5-24 Front view of the Hewlett-Packard FC Switch 108

Figure 5-25 Back view of the Hewlett-Packard Fibre Channel Switch 108

Figure 5-26 Example of FC Switch Configuration 110

Figure 5-27 Hewlett-Packard FC Mass Storage Topology 112

Figure 5-28 Hewlett-Packard FC Mass Storage Topology 113

   


Fibre Channel for Mass Storage
Fibre Channel for Mass Storage
ISBN: B000OHG7EW
EAN: 2147483647
Year: 1999
Pages: 53

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