Figure 7.3: Conceptual views of variable gain amplifiers: (a) switch-control type, (b) two-stage LNA–VGA type
Figure 7.4: A single-ended fully tuneable (gain and frequency) low-voltage LNA
Figure 7.5: Conditions for input impedance matching
Figure 7.6: Micrograph of the 5.8 GHz CMOS LNA
Figure 7.7: Measured power gain of the single-ended 5.8 GHz CMOS LNA with a 1 V supply
Figure 7.8: Measured (a) input and (b) output reflection coefficients of the 5.8 GHz CMOS LNA
Figure 7.9: Gain tuning of the 5.8 GHz CMOS LNA
Figure 7.10: Measured power gain of the 5.8 GHz CMOS LNA with a power supply of 0.7 V
Figure 7.11: Frequency tuning of the 5.8 GHz CMOS LNA
Figure 7.12: Capacitance tuning characteristics and quality factor of the varactors
Figure 7.13: Micrograph of the 9 GHz CMOS LNA
Figure 7.14: Measured power gain of the (a) 8 GHz and (b) 9 GHz CMOS LNAs
Figure 7.15: Measured power gain of the (a) 8 GHz and (b) 9 GHz CMOS LNAs with a power supply of 0.7 V
Figure 7.16: Gain tuning characteristics of the 8 and 9 GHz CMOS LNAs
Figure 7.17: (a) Complementary differential LC VCO structure [12]; (b)–(d) progression towards a low-voltage topology
Figure 7.18: Comparison of supply voltage and power consumption versus frequency of state-of-the-art VCOs
Figure 7.20: (a) Tank components for the circuit in Figure 7.19, and (b) high frequency equivalent circuit
Figure 7.23: Frequency tuning versus (a) back-gate voltage, and (b) PMOS tank bias current. The two diamond points on the top figure show the minimum and maximum achievable frequencies, when both tuning schemes are combined
Figure 7.19: Circuit of the proposed VCO using capacitively coupled NMOS-PMOS LC tanks. The output buffers are on-chip PMOS transistors with 50 Ω resistor loads. V-freq-tun: Back-gate control voltage for frequency tuning. I-freq-tune: Bias-current control voltage for frequency tuning
Figure 7.21: Micrograph of the 8.7 GHz VCO
Figure 7.22: Measured single-ended outputs of the (a) 8.7 GHz and (b) 10 GHz VCOs
Figure 7.24: Output power variation of the 8.7 GHz VCO as a function of both the back-gate and bias current of the PMOS tank
Figure 7.25: Comparison of the figure of merits of the VCOs presented in this work to that of state-of-the-art
Figure 7.26: Comparison of proposed VCOs tuning ranges to state-of-the-art
Figure 7.27: Receiver architecture
Figure 7.28: The differential LNA used in the receiver
Figure 7.29: Schematic of the I/Q mixer
Figure 7.30: Schematic of the quadrature VCO
Figure 7.31: Receiver chip photomicrograph
Figure 7.32: Printed circuit board test setup for the receiver
Figure 7.33: Input reflection S11 of the receiver
Figure 7.34: Receiver output spectrum for a two-tone test response, without calibrating out the test set-up losses
Figure 7.35: Receiver measured third-order intercept plot, after calibrating out the test set-up losses
Chapter 8: Design of Integrated CMOS Power Amplifiers for Wireless Transceivers
Figure 8.1: Conjugate match and load-line match
Figure 8.2: Compression characteristics for conjugate match (S22) (solid curve) and power match (dotted curve). 1 dB gain compression points (B′, B) and maximum power points (A′, A) show similar improvements under power-matched conditions
Figure 8.3: Effect of the knee voltage on the determination of the optimum load
Figure 8.4: Traditional illustration of the schematic and associated current wave-forms of classes A, B, AB and C
Figure 8.5: (a) RF power and efficiency as a function of the conduction angle; (b) Fourier analysis of the drain current
Figure 8.6: Waveforms of a switching-mode power amplifier with hard switching
Figure 8.7: (a) Typical schematic of a class E power amplifier; (b) its voltage and current waveforms showing the soft switching characteristics
Figure 8.8: A simplified class E power amplifier, and its steady state operation
Figure 8.9: Single-ended class E resonant power amplifier
Figure 8.10: Schematic diagram and output waveform of a typical class F stage
Figure 8.11: Classical definition of power amplifier classes
Figure 8.12: (a) Simple feedforward topology, (b) addition of delay elements
Figure 8.14: Conceptual diagram of envelope elimination and restoration technique
Figure 8.15: Linear amplification using non-linear stages
Figure 8.16: Spectral regrowth due to amplifier non-linearity
Chapter 9: Parasitic-Aware RF IC Design and Optimisation
Figure 9.1: (a) Cross-sectional and (b) top views of a parasitic-laden monolithic square spiral inductor
Figure 9.2: Typical measured frequency response of an on-chip square spiral inductor
Figure 9.3: Parasitic values (see Figure 9.1) versus inductance for on-chip square spiral inductors. The dark circles represent values extracted from measurements using the ‘three bears’ modelling approach. The ‘x’ values are obtained using a calibrated EM simulator
Figure 9.4: A typical bond wire inductor with parasitics
Figure 9.5: Local minima (A and C) and a global minimum (B) for a simple cost function
Figure 9.6: Typical flow chart for gradient descent optimisation
Figure 9.7: Flow chart of the parasitic-aware simulated annealing optimisation methodology
Figure 9.8: Flow diagram of the inner loop of the parasitic-aware simulated annealing algorithm
Figure 9.9: (a) Hill climbing in simulated annealing, and (b) the tunnelling process in adaptive simulated annealing for a cost function versus design variable, X
Figure 9.10: (a) Conventional simulated annealing, and (b) adaptive simulated annealing results for a cost function versus a design variable, x
Figure 9.11: Flow chart of simulated annealing with tunnelling process
Figure 9.12: Weighted vector sum of previous and random directions for determining the direction to the next simulation point
Figure 9.13: The relation between slope of the cost function and Temp coefficient
Figure 9.14: The block diagram of adaptive temperature coefficient heuristic
Figure 9.15: Block diagram of post-optimisation PVT variation analysis
Figure 9.16: Probability of finding the global minimum versus Maxloop for conventional versus adaptive simulated annealing
Figure 9.17: Probability of finding the global minimum versus m
Figure 9.18: Probability of finding the global versus tunnelling radius for conventional versus adaptive simulated annealing
Figure 9.19: Basic circuit topology of a class-E power amplifier and its associated waveforms
Figure 9.20: Three-stage CMOS power amplifier (class-AB, class-E, class-E) showing gain and drain efficiency (η) distribution
Figure 9.21: The number of iterations required to find the optimum solution for simulated annealing without and with tunnelling (12 synthesis runs) with power amplifier
Figure 9.22: Cost function trajectory versus the number of iterations in (a) conventional and (b) adaptive simulated annealing with tunnelling. Note the different x-axis scales
Figure 9.23: Simulation results with ideal inductors, and parasitic-laden inductors before and after optimisation
Figure 9.24: Four-stage CMOS distributed amplifier with artificial LC gate and drain delay lines
Figure 9.25: The number of iterations required to find the optimum solution for simulated annealing without and with tunnelling (12 synthesis runs) for the distributed amplifier
Figure 9.26: Cost functions versus the number of iterations in conventional and adaptive simulated annealing with tunnelling
Figure 9.27: (a) Forward gain (S21(dB)) magnitude and (b) forward gain phase results
Chapter 10: Testing of RF, Analogue and Mixed-Signal Circuits for Communications—an Embedded Approach
Figure 10.1: Sample signal spectra at (a) the input of a receiver and (b) the output of a transmitter. Linearity, frequency selectivity, noise performance and other performance requirements can easily be described through direct observation of such spectra
Figure 10.2: Generic flow of a simulation-based defect-oriented test methodology. Several variations exist. Problems with this approach include a general disagreement on the implementation of each of the steps in this methodology as well as its applicability to predicting post-manufacturing effects
Figure 10.3: (a) A DSP-based spectrum analyser. (b) Similar spectrum analyser capable of characterising higher-frequency signals by shifting them down to the frequency range of the ADC
Figure 10.4: ATE integration of DSP-based measurement instruments. Central processing and control are used, and an automatic signal handling mechanism is incorporated
Figure 10.5: Block diagram of a generic mixed-signal automatic tester [6]
Figure 10.6: Block diagram of proposed on-chip test system
Figure 10.7: A more detailed view of the integrated test system architecture
Figure 10.8: Frequency spectrum of a periodically repeating ΣΔ modulated sequence encoding a single sine wave. The sequence length in this example was 1024
Figure 10.9: Exploiting the periodicity of the input signal to perform multiple digitisation passes. UTP = Unit Test Period
Figure 10.10: (a) Converting the comparator into a digital latch to verify functionality. (b) Replicating the DC generator allows for a quick method of sweeping comparator terminals
Figure 10.11: Test core bypassing CUT in order to measure the analogue reconstruction filter (clocking system not shown for clarity). The response (b) to a multitone signal (a) can be captured using an integrated digitiser (c) in order to predict filter behaviour
Figure 10.12: Implemented comparator consisting of a single-pole low-gain linear amplification stage followed by a positive feedback (non-linear gain) latch [34]. No offset correction was necessary for target resolution
Figure 10.13: Implemented sample-and-hold amplifier. Tracking bandwidth is determined by the RC time constant of the switch on-resistance and the sampling capacitor
Figure 10.14: Measured spectrum of a ΣΔ modulated stream at 250 MHz as seen on a HP3588A spectrum analyser. The dashed curve is an envelope of actual programmed frequency bin power in the software. Very few spurious tones (i.e. deviations from this envelope) are apparent in the measured result
Figure 10.15: Measured spectrum of a ΣΔ stream at 250 MHz as seen on a HP3588A spectrum analyser. Filtering is performed externally using a discrete bandpass filter. The dashed curve is programmed tone power in software. Few spurious tones are apparent in the measured result
Figure 10.16: FFT-based spectral estimate of a digitised sine wave that is generated using the on-chip arbitrary waveform generator
Figure 10.17: Sample result for a sine wave at 20.001 MHz digitised at a 20 MHz clock rate. (a) Power spectral density, (b) time-domain plot
Figure 10.18: Digitiser performance as a function of test signal frequency. The observed performance is similar to some of the best published data converter performance in the same technology [36]
Figure 10.19: Experimental result of a DC voltage sweep applied to an external
Figure 10.20: Experimental result demonstrating frequency response measurement of a lowpass filter using multitone signals. A multitone signal containing five tones was generated using our test core, and the filter response to the tones was digitised and processed
Figure 10.21: Spectral plot illustrating total harmonic distortion, SFDR, or SNR measurement
Figure 10.22: Time-domain waveform illustrating an internally digitised on-chip sine wave. This and other measurements are useful not only for production purposes, but also for debug, diagnosis and design characterisation
Figure 10.23: Captured rectangular waveform running at 25 MHz. Delayed-clock subsampling was used in order to achieve an effective sample rate of 1.6 GHz in a 0.35 μm CMOS process
Figure 10.24: Illustration of an eye-diagram measurement. A long pseudo-random digital signal was passed through a lowpass filter to emulate a lossy channel. The output of the filter was sampled using the proposed test cores at a rate of 1.6 GHz
Figure 10.25: Experimental setup used to demonstrate socket/board test applications involving time-domain measurements. The probe connection to the oscilloscope was included to verify the setup
Figure 10.26: Experimental time-domain reflectometry measurement. The termination resistor in this case is an open-circuit. (-) Integrated prototype, (–) Tektronix TDS8000 digital sampling oscilloscope with 40 GHz sampling head
Figure 10.27: Repetitively observing the time a signal crosses a fixed threshold reveals statistical information about the underlying variability in the signal period, or jitter. Many edges have to be captured and their relative frequency of occurrence over fixed sample instances compared
Figure 10.28: Sample jitter measurement. Edge occurrences at the different sampling instances are accumulated in order to obtain a representation of the jitter distribution function. In this example, sampling instances were spaced at 0.1 ns apart