10.3 Translating design specifications into production test programmes


10.3 Translating design specifications into production test programmes

Much of the recent mixed-signal test research falls under the category of reducing test time. The reason is that specification testing, although foolproof, can be extremely time-consuming. Section 10.2 described some of the analogue specifications for mixed-signal circuits. A quick look at the data sheet of a commercial mixed-signal device would reveal that these as well as other specifications also span a wide range of input and environmental (such as power supply and operating temperature) conditions. Testing all of these conditions for all specifications during production would be slow. The question then is whether a simplified set of signals or input conditions can be used to excite the DUT and uncover most of the failures that could occur during fabrication.

Traditionally, this question has been answered through an empirical approach in which a reasonably large number of fabricated devices are subjected to full specification tests. The results of this procedure are then used to compile a short list of tests that fail most of the defective parts. Over the rest of the product life for the part, only the tests in this trimmed list are applied to the DUT and used to screen the faulty devices, and redundant tests are simply omitted. Moreover, it is also conceivable that there be significant correlation between tests [7] and that more than one test fails the same faulty device. Recognising this, early work in mixed-signal circuit testing consisted of methods for not only reducing the test list in the manner just described but for also choosing an order in which tests are applied. As such, the test that is most likely to fail is applied first, followed by less likely ones. Various methods for ordering and trimming the tests include those in References 8–10. Beyond the above methods, a significant portion of the published literature on mixed-signal testing attempts to perform such test list trimming without actually exhaustively testing a subset of the fabricated devices. These approaches can be described within the scope of the flow diagram of Figure 10.2, although depending on the method, one or more of the nodes in this diagram might not be needed. Assume for the time being that we know all defects that can affect the DUT. In these methods, the layout of the circuit under test is modified according to the effects of these defects, the new extracted circuit is simulated, and the response of this new ‘faulty’ circuit is compared to the response of the original one. Depending on the input conditions and the resulting response comparison, some test signals can be found to be ‘useful’ in detecting manufacturing defects, while others are deemed not useful [7]. As can be seen, the result of the above procedure is a short set of test stimuli (DC, AC, or transient) that need to be applied to a DUT during the actual test phase and a second set of expected ‘signatures’ or circuit responses that can distinguish between a good part and a bad part. The size of the set is usually kept to a minimum in these techniques. For example, in Reference 11, only a few DC levels out of thousands are used to test an A/D converter.

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Figure 10.2: Generic flow of a simulation-based defect-oriented test methodology. Several variations exist. Problems with this approach include a general disagreement on the implementation of each of the steps in this methodology as well as its applicability to predicting post-manufacturing effects

While conceptually appealing, the above procedure for test selection is marred with hurdles that have hindered its progress over the past. These include the difficulty in defining what a defect or fault is for analogue components [12] and modelling inaccuracy associated with simulating the virtual defective devices [13]. Several attempts have been made to address these difficulties with varying degrees of success. The interested reader is referred to References 9, 10, 14, 15 for different approaches to modelling defects and their effects on analogue circuits and to References 16–18 for some approaches to simulating the effects of these defects. Finally, the test stimulus generation node in Figure 10.2 has also been the subject of extensive research. Two representative approaches to test pattern generation are included in References 19 and 20.




Wireless Communication Circuits and Systems
Wireless Communications Circuits and Systems (IEE Circuits, Devices and Systems Series 16)
ISBN: 0852964439
EAN: 2147483647
Year: 2004
Pages: 100
Authors: Yichuang Sun

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