6.2 Filters in transceivers and the need for tuning


6.2 Filters in transceivers and the need for tuning

This section outlines the role of filters in typical wireless transceiver architectures, and some of the important parameters in their design. The need for on-chip tuning in virtually all practical applications of integrated filters is then discussed.

6.2.1 Filter requirements for wireless transceivers

A typical single-chip wireless transceiver design requires several different filters; possible architectures for a receiver and transmitter are shown in Figures 6.1 and 6.2 respectively [3]. In Figure 6.1, the signal input from the antenna is bandpass filtered at the signal frequency, typically in the VHF/UHF range. This defines the bandwidth of the receiver frontend, and reduces unwanted responses, such as the image response in the case of the superheterodyne architecture. Many designs rely on impedance matching networks associated with the low-noise amplifier to provide sufficient selectivity, but in more demanding applications additional filters are require. The majfor challenge or integrated RF filter design is the high operating frequency; for example, GSM handsets operating around 900 MHz, Bluetooth at 2.45 GHz. Operation at these frequencies pushes the capabilities of current IC technologies, and circuit parasitics have a serious adverse effect on the response of the filter, making predictable performance difficult to achieve.

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Figure 6.1: Typical receiver block diagram for wireless transceiver

The signal is then down-converted to an intermediate frequency (IF), where further bandpass filtering occurs. Traditionally, the IF bandpass filter performs the channel filtering function before the signal is demodulated; in modern receiver designs this function is shared with subsequent digital signal processing. Each IF filter acts as an anti-aliasing filter for the succeeding converter or demodulator, and by providing rejection of unwanted signals in adjacent channels it reduces the dynamic range of signals applied to the ADCs. The bandwidth of the IF filters is defined by the type of modulation used; in multistandard receivers it may be necessary to provide a filter with selectable bandwidths. A low-IF architecture is shown in the example, with an image-rejection mixer. This architecture requires low-Q bandpass filters, with a centre frequency of similar order of magnitude to the bandwidth. Typical centre frequencies and bandwidths range from hundreds of kilohertz to several megahertz. As an alternative to the separate I and Q channel IF filters and ADCs shown, a single converter may be used in conjunction with a polyphase, complex bandpass filter which performs the image rejection function [4].

As with the other circuit functions in the receiver signal path, the filters will directly contribute noise and non-linearity. Thus as well as meeting specified requirements for amplitude, group delay, etc., the dynamic range of these filters is of critical importance.

The low-IF architecture is currently the most popular for wireless transceiver designs. Other receiver architectures may also be used. In the direct conversion (‘zero IF’) architecture, the incoming signal is converted directly to baseband, using a similar scheme to Figure 6.1, but with the IF bandpass filters replaced by low-pass filters. The cut-off frequcncy is then determined by the modulation bandwidth. The traditional superheterodyne design uses an IF frequency much larger than the signal bandwidth; this requires a high-Q, high-frequency, bandpass filter, and usually additional frequency conversion stages.

Many recent receiver designs digitise the received signal, and use a DSP ‘backend’ to perform further signal processing and demodulation at low IF or baseband frequencies. Many wireless communications systems also require analogue outputs, for example audio signals. These require reconstruction filters at the DAC outputs.

The transmitter architecture of Figure 6.2 reverses the signal flow path of the receiver. The modulated signal is generated by DSP, and up-converted to the signal frequency. Again, anti-aliasing and reconstruction filters are required for the data converters. RF filtering at the output frequency is also required to suppress unwanted mixing products generated by the up-conversion process. The linearity and dynamic range requirements for filters in the transmit signal path are more relaxed than in the receiver because the transmitter operates over a relatively narrow range of signal levels.

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Figure 6.2: Typical transmitter block diagram for wireless transceiver

Therefore, we see that a typical transceiver contains several filters operating over a very wide frequency range, from input frequencies in the gigahertz range to audio reconstruction filters. Several different active filter techniques are often used within the same transceiver to suit these differing requirements. These are discussed in more detail in Section 6.3.

6.2.2 The need for on-chip tuning

On-chip tuning is essential for most filters because of the extremely wide tolerances of components fabricated in the IC processes normally used for the fabrication of the mixed-signal ‘system on a chip’ (SoC). In terms of volume, the vast majority of ICs being manufactured currently are digital in nature, and as a result, CMOS processes optimised for digital logic are the most highly developed and economical for high-volume, low-cost production. Because most wireless transceiver applications are very cost-sensitive, and the analogue RF parts of these transceivers represent only a small proportion of the total circuitry on the chip, an overwhelming economic case exists for using CMOS digital processes for the implementation of the complete transceiver. From the viewpoint of the analogue designer, CMOS processes, whilst yielding active devices capable of excellent high-speed performance, are mediocre from the point of view of component value accuracy. Each type of component is fabricated during several process steps, each of which contributes variability to the final component value.

Typically, initial component tolerances of the order of several per cent to tens of per cent can be expected. It is interesting to note that, in spite of the great strides made in semiconductor technology during the past few decades, component tolerances have improved little [5]. It is possible to fabricate accurate on-chip components, but the need for extensive additional processing makes this impractical for applications where high yield and low cost are of paramount importance. The pole and zero frequencies of the filter are dependent on the values of at least two different types of component, for example, resistance and capacitance or transconductance and capacitance, each of which is subject to uncorrelated tolerance variations. Therefore, tolerances on the initial cut-off or centre frequencies of the filter of 50 per cent or more can be expected.

In principle, the desired filter response could be obtained by trimming components on the die after fabrication. However, this is usually impractical for economic reasons. In standard IC processing, a large number of chips are processed in parallel, as a single operation, simultaneously on a single wafer. This is a fundamental factor that allows production of complex ICs at very low cost. On the other hand, a postfabrication trimming process would have to be performed on each die individually, adding significantly to test times and so to production cost. Also, even after trimming, the components on the IC are subject to further substantial variations in value due to the effects of ageing and environmental variables, in particular temperature.

Therefore, a viable fully integrated filter design for a wireless transceiver requires some form of on-chip automatic tuning system. The filter itself is built from electrically tuneable voltage- or current-controlled elements, and tuning control circuits adjust the tuning signal values until the required response to a reference signal is obtained. This firstly requires filter circuit structures that are electrically tuneable over a sufficient range to compensate for component tolerances, whilst at the same time capable of meeting all system design requirements for filter response, dynamic range, etc. Suitable circuit techniques that have been exploited include gm-C, MOSFET-C and active-LC; these are discussed in Section 6.3. Secondly, a tuning system must be devised which is capable of detecting whether the filter response is correct within acceptable limits, and if not, apply suitable corrections to the tuning signals to restore correct operation. Because changing chip operating conditions lead to significant changes in filter performance, the tuning process must usually proceed continuously, or periodically at frequent intervals during normal operation of the chip, without upsetting the operation of the system as a whole. A wide range of on-chip tuning methods have been devised; some of these are discussed in Section 6.4




Wireless Communication Circuits and Systems
Wireless Communications Circuits and Systems (IEE Circuits, Devices and Systems Series 16)
ISBN: 0852964439
EAN: 2147483647
Year: 2004
Pages: 100
Authors: Yichuang Sun

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