2.3 Digitising a conventional low-IF architecture


2.3 Digitising a conventional low-IF architecture

The diagram given in Figure 2.4 illustrates a low-IF receiver architecture [5] with a still higher level of digitisation than that shown in Figure 2.3. At the frontend it comprises the usual combination of RF filter, low-noise amplifier and quadrature down-converter for capturing the incoming RF signals and placing the wanted channel on the IF of 100 kHz. To remove the troublesome DC offsets generated in the mixers, the I and Q components of the IF signal pass through a pair of AC couplings which act as first-order highpass filters with a cut-off frequency of approximately 10 kHz. The cut-off frequency is not critical but this value is high enough to allow the removal of DC offsets without damaging the wanted signal. As shown in the figure, the IF signals are amplified by two fixed-gain elements and then fed directly into a complex ADC. The need for AGC has therefore been eliminated. The ADC is complex to align the spectrum of its quantisation noise with that of the wanted signal. It is realised as a pair of cross-coupled ΣΔ modulators which digitise the I and Q inputs into a pair of bit streams of 1-bit resolution. These are in turn filtered by the digital channel filter whose dual roles are to remove any external interferers accompanying the wanted signal and also to remove the high-frequency quantisation noise generated by the ADC.

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Figure 2.4: Complex signal processing in a low-IF receiver architecture

There can be little doubt that eliminating the need for analogue channel filtering and AGC in this way is a significant step forward in terms of giving the receiver better multimode potential. However, moving the ADC function to such an advanced position in the signal chain carries the disadvantage of increasing the dynamic range requirement of the ADC. As will be explained later, the dynamic range required for GSM in these circumstances is in the region of 100 dB and when this is combined with the complex aspect of the signal processing, the design of the ADC becomes a major challenge. There is also the disadvantage of needing a total of four FIR filter blocks in order to realise the asymmetrical frequency characteristics of the complex channel filter.




Wireless Communication Circuits and Systems
Wireless Communications Circuits and Systems (IEE Circuits, Devices and Systems Series 16)
ISBN: 0852964439
EAN: 2147483647
Year: 2004
Pages: 100
Authors: Yichuang Sun

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