Chapter 2: Non-Complex Signal Processing in a Low-IF Receiver


Brian J. Minnis, Paul A. Moore

2.1 Introduction

Cellular radio telephone handsets are now in common use throughout the world. The resultant commercial pressure for compact and low-cost products has led to renewed global research interest in receivers and the consequent development of highly integrated solutions based on architectures that might otherwise have languished as mere curiosities. The resultant widespread acceptance of zero-IF (intermediate frequency) and low-IF receivers in handsets for GSM (Global System for Mobile communications) has taken integration to a level from which any further significant improvement is now hard to imagine. But the additional need to address new, third-generation (3G) standards, such as UMTS (Universal Mobile Telecommunication System), is tending to re-focus research activities in this area towards increased flexibility and the maximisation of hardware re-use. This is most easily addressed by increasing the level of digitisation. However, unless this is handled intelligently, power consumption can easily be increased over and above that used by existing analogue implementations, with unacceptable consequences in terms of battery life. Hence, we present a novel architectural solution to this problem, mainly in the context of GSM but which forms part of a multimode receiver for both GSM and UMTS.

After describing the evolution of integrated receiver architectures that can be applied to GSM, this chapter will discuss the digitisation problem in a little more detail, examine the basic performance requirements and derive some of the most important receiver dimensions. It will then present a revised low-IF receiver architecture in which the need for a complex analogue-to-digital converter (ADC) is avoided. The technique involves dropping the Q component of the IF output of the frontend and then only processing the I component in the ADC. Details will be given of the three blocks most closely associated with the non-complex signal processing, namely the polyphase image-rejection filter, the digital make-complex filter and the ADC itself which is based on a fifth-order sigma-delta (ΣΔ) modulator. System simulations will be described and the results derived from them will be presented in validation of the modified architecture. The chapter will then discuss the incorporation of the new approach into the multimode receiver for GSM and UMTS before drawing some final conclusions.




Wireless Communication Circuits and Systems
Wireless Communications Circuits and Systems (IEE Circuits, Devices and Systems Series 16)
ISBN: 0852964439
EAN: 2147483647
Year: 2004
Pages: 100
Authors: Yichuang Sun

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