memory systems. This is due to the fact that the memory bandwidth internal to the memory chip is far greater than that delivered to the system bus at its pins. Significant advances in delivering these internal acquired bits to the system bus in rapid succession have been manifest in such memory types as Extended Data Output DRAM (EDO-DRAM) and Synchronous DRAM (SDRAM). Common access times are 70, 60, and 50 nanoseconds for main memory (DRAM). SDRAMs can deliver 8 bytes every 10 nanoseconds, making them the preferred component for newer high-speed buses. Further improvement to the apparent performance of the entire memory system as viewed by the processor comes from mixing small memories of fast technology with high capacity memory of slower technology.
3.4.3 Memory Types
Semiconductor memory revolutionized the cost and capacity of memory systems, breaking the 20 year dominance of magnetic core technology in the mid 1970s. Semiconductor memory is available in two fundamental types. Static random access memory or SRAM is high speed but moderate density while dynamic random access memory or DRAM provides high density storage but operates more slowly. Each plays an important role in the memory system of the Beowulf node.
SRAM SRAM is implemented from bit cells fabricated as multi-transistor flipflop circuits. These active circuits can switch state and be accessed quickly. They are not as high density as are DRAMs and consume substantially more power. They are reserved for those parts of the system principally requiring high speed and are employed regularly in L1 and L2 caches. Current generation processors usually include SRAMs directly on the processor chip. L2 caches may be installed on the motherboard of the system or included as part of the processor module.
Earlier SRAM was asynchronous or ASRAM and provided access times of between 12 and 20 nanoseconds. Recent motherboards operating up to 66 MHz used synchronous burst SRAM or SBSRAM providing access times between 8.5 nanoseconds and 12 nanoseconds. The high speed processors being employed as Beowulf nodes use pipelined-burst SRAMs or PBSRAM with access times of 4.5 to 8 nanoseconds.
DRAM DRAM is implemented from bit cells fabricated as a capacitor and a single by-pass transistor. The capacitor stores a charge passively. The associated switching transistor deposits the state of the capacitor's charge on the chip's internal memory bus when the cell is addressed. Unlike SRAM, reading a DRAM cell is destructive, so after a bit is accessed the charged state has to be restored by
