4.2 Second-Generation HDSL (HDSL2)

   


The primary goal of second-generation HDSL, hereby referred to as HDSL2, is to utilize the advancements in integrated circuit design to develop a digital subscriber line transmission system that transports a DS1 payload on a single wire pair on loops that meet carrier serving area (CSA) requirements. This objective has the same deployment coverage as conventional HDSL that uses two wire pairs. Figure 4.13 shows a provisioning diagram of a T1 access circuit provisioned using second-generation HDSL technology. Although the core technology for the transceivers is more complex than that for first-generation HDSL, the total provisioning and equipment costs will be lower than for conventional HDSL when deploying service on a single wire pair as opposed to two pairs.

Figure 4.13. Provisioning of T1 service using HDSL2.

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Given that core second-generation transceivers can support the transmission of twice the bit rate at the same distance as the first-generation transceivers, an extension of this new technology should allow transmission of the original bit rate at a significantly greater distance than the first generation technology. Hence, we expect to be able to deploy dual-duplex HDSL using the new technology at distances significantly greater than CSA.

The following sections describe the HDSL2 technology in detail. We also provide some background in the development of the new approach for HDSL transmission. The complete HDSL2 standard is defined in T1.418 [8].

4.2.1 Performance Objectives for HDSL2

Although the HDSL2 project began in 1995 [16], industry interest did not take affect until 1996. At that time, the operators provided a list of requirements and objectives for DS1 transport on a single wire pair [17], [18]. Based on feedback from feasibility studies, the requirements were revised [19], [20], [21]. A summary of the performance requirements and objectives are as follows :

  • Loop Reach : CSA Requirements (i.e., 9 kft 26 AWG and 12 kft 24 AWG)

  • Performance against crosstalk impairments : minimum of 5 dB margin with one percent worst case crosstalk from the following interfering signals

    • 49 HDSL

    • 39 HDSL2

    • 39 Echo canceled (EC) ADSL

    • 49 Frequency-division multiplexed (FDM) ADSL

    • 25 T1 AMI disturbers

    • 24 T1 + 24 HDSL2

    • 24 FDM-ADSL + 24 HDSL

  • Spectral Compatibility : In general, the goal for spectral compatibility of HDSL2 is to not disturb all existing DSL services more than what is tolerated from other services at the time of the development of the technology. However, based on feasibility study and market need, the following exceptions were agreed:

    • HDSL2 shall not degrade HDSL [4] by more than 2 dB [22], [23]

    • HDSL2 shall not degrade ADSL [12] by more than 1 dB [24]

  • Latency : The maximum latency for HDSL2 is 500 m sec.

HDSL2 was the first DSL standards development to address crosstalk from mixed sources (e.g., the last two interferer models in the list above). Because the mixed noise model is more severe than the traditional consideration of only homogeneous noise, it was considered appropriate to design HDSL2 for a 5 dB margin instead of the traditional 6 dB margin.

4.2.2 Evolution of the Modulation Method for HDSL2

Numerous modulation methods (or line codes) were considered as possible candidates for HDSL2 prior to the selection of sixteen-level trellis code pulse amplitude modulation (TC-PAM). In order to gain significant performance over the 2B1Q line code for HDSL, the general approach taken for performance improvement in the modem signal processing is to use a high-state trellis code with channel precoding. In addition, special spectral shaping would be required to find the proper balance between performance and spectral compatibility with other signals in the cable. The upstream and downstream channels would share common frequencies so the duplexing method for HDSL2 would be echo cancellation. Figure 4.14 shows the generalized functional block diagram of the transceiver structure for HDSL2. Note that this block is applicable for baseband systems such as PAM and single-carrier passband systems such as QAM or CAP.

Figure 4.14. General transceiver functional block diagram for HDSL2.

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Early on in the development of HDSL2, the line codes considered for HDSL2 were multilevel PAM and multilevel CAP (or QAM). At first, all of the systems considered had used symmetric upstream and downstream spectra with the bandwidth set to one-half the symbol rate for the PAM-based systems and equal to the symbol rate for the CAP/QAM systems. The performance of all these systems was limited by self near-end crosstalk (SNEXT), and the best configuration of each system fell about 2 to 3 dB short of the requirements [38], [39], [41], [42]. The SNEXT limitation needed to be overcome by some method in order to meet or get close to meeting the objective requirements.

An alternative to using fully overlapped symmetric spectra is to use frequency-division multiplexing (FDM) of the upstream and downstream signal spectra. If the upstream and downstream spectra were totally nonoverlapping, then there would be no SNEXT. The performance limitation would be NEXT from other systems or self far-end crosstalk (SFEXT) from other similar systems. Although the latter case is certainly preferable, in a multiservice cable environment there will be a mixture of overlapped and nonoverlapped signal spectra in the cable. Also, the higher frequency band in an FDM system would be susceptible to greater loop attenuation because of its placement at higher frequencies. Crosstalk coupling is also greater at the higher frequencies, so crosstalk impact to other services needs to be considered. Hence, the spectrum design of HDSL2 must be such that it operates in numerous NEXT and FEXT crosstalk environments. An early proposal that considered these issues was that of a " staggered FDM" scheme described in T1E1.4/96-340 [25].

In T1E1.4/97-073 [26], partially overlapped echo-canceled transmission (POET) was proposed, which involved overlapping nonidentical upstream and downstream spectra. The spectra were carefully shaped so as to maximize performance in the presence of crosstalk and to minimize the spectral compatibility impact into other services in the cable. Other approaches working off of the same core principle included POET-PAM [26], OverCAPed (oversampled CAP/QAM) [27], OPTIS [28], [29], and MONET [30], [31].

Most of the modulation schemes later proposed had PSDs with boosted energies at higher frequencies that were above their nominal low-frequency values. Testing of HDSL systems in the presence of crosstalk from systems using the OPTIS shaping showed significant impact on the performance of the HDSL. Based on this testing, the OPTIS spectra were modified such that their spectral compatibility impact on HDSL would be less than 2-dB of degradation. The network operators in North America unanimously agreed upon this degree of degradation. The resulting PSDs adopted for HDSL2 are shown in Figure 4.23 for the downstream channel and Figure 4.24 for the upstream channel.

Figure 4.23. Downstream channel spectrum.

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Figure 4.24. Upstream channel transmit spectrum.

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One element introduced in the evaluation of the above proposals is that of decoupling of the transmit signal bandwidth from the symbol rate, so that the bandwidth of the PSD could have significant energy in bandwidth greater than that determined directly by the symbol rate. An implication of such an approach would require the use of oversampling in the transceiver design, particularly in the receiver where at least a 2x or 3x sampling would be required, depending on the modulation approach chosen . The benefits of this decoupling were found in T1E1.4/97-237 [28] when measuring the performance of proposed HDSL2 spectra in the presence of mixed crosstalk for PAM-based systems. This extension of the bandwidth showed particular benefit to the PAM approach under certain conditions of mixed crosstalk in the downstream channel. With a conventional DFE, the alias terms of the PAM spectrum reflect back at half the PAM symbol rate. With the excess bandwidth of the downstream OPTIS spectrum (i.e., the portion of the downstream spectrum above the overlapped upstream-downstream region), the folding is such that this region fills the area of poor SNR due to NEXT from the upstream region.

The CAP/QAM system is processed as an analytic signal (i.e., a complex signal having only positive frequency components ), and it folds in a nonreflective manner at the symbol rate. With the OPTIS spectrum, the folding does not benefit the passband system as it does the baseband PAM system because the frequencies that fold into the SNR-poor high end of the passband are substantially higher in frequency. The result is that with the OPTIS spectrum, the downstream channel administers 3 to 4.5 dB better performance in mixed crosstalk containing T1 AMI disturbers for the PAM system than for the CAP/QAM-based system. It was for this region that the PAM line code was chosen over CAP/QAM for HDSL2.

In summary, the core of the HDSL2 transceiver uses the OPTIS PSD with the PAM line code. The shape of the transmit spectrum is decoupled from the symbol rate to allow for flexible use of the excess bandwidth. The excess bandwidth provides improved performance in the downstream channel against mixed crosstalk that contains T1 AMI. The selected PAM configuration uses 3 information bits per symbol, which corresponds to an eight-level signal. The unique spectral shaping of OPTIS is the best compromise found in optimizing the performance against crosstalk in the loop plant and maintaining spectral compatibility with other systems. The nominal transmit power for the upstream channel is 16.5 dBm and that for the downstream channel is 16.8 dBm. This modulation technique was shown (using ideal DFE calculations) to have a minimum of 1.0 dB of margin on the worst-case test loop. In order to achieve the highly desired objective of 6-dB margin against worst-case crosstalk, an advanced coding mechanism with a minimum coding gain of 5 dB is required. It was agreed to use a high order trellis code to help achieve the objective margin. The following sections provide an overview of the configuration defined in HDSL2 standard T1.418 [8].

4.2.3 System Reference Model

As with first-generation HDSL, the driving application is to provision a T1 access circuit on loops that meet the carrier serving area requirements. Figure 4.15 shows the system reference model for an HDSL2 transceiver unit. This is very similar to that of HDSL except that core transceiver provides transmission on a single wire pair.

Figure 4.15. System reference model for and HDSL2 transceiver unit.

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The payload interface for HDSL is that of a T1 AMI signal. In the CO, the interface is a DSX-1 interface that is defined in AT&T compatibility bulletin CB-119. At the customer premises, Committee T1 Standard T1.403 [11] defines the T1 AMI interface.

The T1 AMI interface circuit terminates the AMI signal and converts the signal into a 1.544 Mb/s bit stream together with the recovered signal clock. The HDSL2 transceiver unit will transport the 1.544 Mb/s payload end to end along with the bit synchronous timing information. Transfer of bit synchronous timing is referred to as pass through timing . This is required for the transparent support of T1 AMI service.

The HDSL2 framer is required for supporting operations, administration, and maintenance functions for the HDSL2 access circuit. The framer adds 8 kb/s of overhead, which provides frame synchronization, performance monitoring, performance indication, and an embedded operations channel (EOC) for communication between the CO and remote HDSL2 units.

The HDSL2 transceiver is the core HDSL2 modem that provides the key modulation and demodulation functions. The following sections describe each of the key blocks in detail as defined in the HDSL2 standard in T1.418 [8].

4.2.4 HDSL2 Framing

The structure of the HDSL2 core frame is based on the super frame structure of first-generation HDSL, except that there is no alignment defined in the HDSL2 standard [8] to the DS1 time slots, nor the DS1 frame for that matter, in the HDSL2 frame. It is generally assumed that synchronization with the DS1 frame is provided separately from the HDSL2 frame.

Figure 4.16 shows the core HDSL2 physical layer frame structure. The nominal frame period (T frame ) is 6 msec. Because the line bit rate is 1552 kb/s (1544 kb/s payload and 8 kb/s overhead), there are nominally 9,312 bits in an HDSL superframe: 9,264 bits are for the DS1 payload and nominally 48 bits are for the overhead functions.

Figure 4.16. HDSL2 core frame structure.

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As shown in the figure, the HDSL2 superframe is broken up into four payload blocks and five overhead blocks. The four payload blocks are labeled PB1 “PB4, and the overhead blocks are labeled OH1 “OH4 and SB. Each payload block contains 2,316 bits. Note that there is no alignment of the DS1 frame or time slots with the HDSL2 payload blocks.

The overhead bits are distributed throughout five overhead blocks. Unlike the payload blocks, the overhead bits are not distributed as evenly across the blocks. Overhead block OH1 has 10 bits, blocks OH2 “OH4 each have 12 bits, and the last block (the stuff bits) may have either 0 or 4 bits. The following is a summary of the overhead bit definitions.

  • OH1 (10 bits) : This block contains a 10-bit frame synchronization word (FSW). The purpose of the definition of the FSW is vendor specific. During preactivation , the transmitter forwards its preferred FSW to the far-end receiver via the specified exchange protocol.

  • OH2 (12 bits):

    • Bits 1 and 2 : crc-1 and crc-2

    • Bit 3 : Stuff bit id (first copy)

    • Bit 4 : Far-end DS1 loss of signal defect (losd) indicator bit. This bit identifies any anomaly or loss of signal associated with the DS1 signal sent from the far end. Under normal conditions, this bit is set to a 1; when an anomaly occurs, the losd bit is set to a 0 in the next superframe.

    • Bits 5 “12 : first 8 bits of the embedded operations channel (eoc01 “eoc08)

  • OH2 (12 bits):

    • Bits 1 and 2 : crc-3 and crc-4

    • Bit 3 : Unspecified indicator bit. This bit is undefined and reserved for future use.

    • Bit 4 : Segment Anomaly (sega) indicator bit. This bit is used to identify any crc-6 errors encountered in the reception of a superframe. The error indication is that associated with the previous superframe. The purpose for this bit is performance monitoring.

    • Bits 5 “12 : second 8 bits of embedded operations channel (eoc09 “eoc16)

  • OH3 (12 bits):

    • Bits 1 and 2 : crc-5 and crc-6

    • Bit 3 : Stuff bit id (second copy)

    • Bit 4 : Segment defect (segd) indicator bit. A repeater sets this bit to a zero to indicate a loss of sync word on an incoming frame. Normally, the end units set this bit to a 1.

    • Bits 5 “12 : third 8 bits of embedded operations channel (eoc17 “eoc24)

  • SB (0 or 4 bits):

    • Bits 1 “4 : Stuff bits

    • Either 0 or 4 stuff bits are inserted in an HDSL2 superframe. The nominal frame is never transmitted; the nominal frame length only appears on average.

The three indicator bits ”losd, sega, and segd ”are transmitted every superframe.

The six CRC bits are used for performance monitoring of the subscriber line. The six CRC check bits, crc-1 “crc-6 are those associated with the contents of the previous HDSL2 superframe. The CRC is computed over all of the bits in the superframe except for the 10 sync word bits, the 6 CRC bits, and the nominally 2 stuff bits; hence, the data message contains 9,294 bits. The message polynomial is constructed such that first CRC computable bit is the coefficient of the term x 9293 , and the last bit is the coefficient of the term x . The polynomial is then multiplied by a factor of x 6 and the result is divided (modulo 2) by the generator polynomial x 6 + x + 1. The coefficients of the remainder polynomial are used in the order of occurrence as the ordered set of check bits crc-1 “crc-6. In the remainder polynomial, the coefficient of the term x 5 is crc-1 and that for the term x is crc-6.

The embedded operations channel has 24 bits allocated in a 6 msec frame. This corresponds to a 4 kb/s clear data communications channel. This channel is used to pass operations and maintenance information between the CO and customer premises HDSL2 transceiver units.

4.2.5 Core Transceiver Structure

Figure 4.17 shows the structure of the HDSL2 core modem transmitter. Accurate definition of these blocks is required in the standard to help assure interoperability of transceivers from different manufacturers. The core transmitter defines the signal processing of the bits coming from output of the HDSL2 framer and the modulated signal output on the subscriber line.

Figure 4.17. HDSL2 transceiver core modem transmitter.

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The scrambler receives the bits at the output of the framer and randomizes the bit sequence so that key adaptive signal processing functions, such as the echo canceler and equalizer, will optimally perform.

The trellis encoder takes the randomized bit stream at the scrambler output and outputs an encoded symbol sequence containing redundancy per a predefined encoding procedure that is determined at initialization. For each transmitted symbol, the trellis encoder collects 3 information bits from the scrambler, adds one additional bit to accommodate the redundancy added by the encoding algorithm, and outputs a 4-bit symbol for transmission on the line. The resulting constellation for the transmit signal has 2 4 = 16 levels; hence the line code name is trellis coded 16-level PAM (16 TC-PAM). When we compare the HDSL2 core transmitter blocks with that of the original HDSL 2B1Q system in Figure 4.5, the trellis encoder takes the place of the bit-to-symbol map function. The trellis encoder together with a Viterbi decoder (or other signal processing efficient decoder) provides the additional coding gain to help meet the system performance objectives.

In an uncoded system, a decision feedback equalizer (DFE) has been shown to provide near optimum performance in the detection of signals. Depending on the channel and noise characteristics, the DFE will provide at least 2 dB of output SNR improvement over linear equalizer. However, when a DFE is used directly with a trellis code, any error propagation through the DFE would significantly degrade any coding gain that is achievable with the trellis code. To achieve the performance gain of both the trellis code and the DFE, the error propagation must be removed. The channel precoder implements the equivalent of a decision feedback equalizer in the transmitter to effectively precode the transmit data prior to transmission on the line. In the transmitter, no decision errors will be made because there is no external injected noise to corrupt the signal. The equalization in the receiver, as shown in generalized transceiver structure of Figure 4.14, is effectively a linear equalizer so there is no error propagation to degrade performance. Details of the channel precoder are provided in a subsection below.

Finally, the spectral shaper is a filter with an impulse response that shapes the transmit signal per the OPTIS spectral shapes shown in Figure 4.23 for the downstream channel and Figure 4.24 for the upstream channel. A typical way of implementing the spectral shaping is to use digital transversal filters with oversampling.

The following subsections discuss the blocks of the core HDSL2 transmitter in more detail.

4.2.6 Scrambler

Figure 4.18 shows the scramble structure of the HDSL2 downstream and upstream transmitters. These scramblers are the same as those defined for HDSL and ISDN.

Figure 4.18. HDSL2 upstream and downstream channel scrambler

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4.2.7 Trellis Encoder

In order to meet the demanding performance objectives of HDSL2, coded modulation is required to increase the immunity to crosstalk encountered in the loop plant. Given the latency requirement of 500 m s, any types of block code or concatenated codes that require interleaving were ruled out because the latency introduced was too large. Interleaved block codes (such as Reed-Solomon codes), concatenated codes with interleaving, and turbo coding techniques proved to be difficult to use because they require latencies significantly greater than 500 m s to meet the performance objective. What remained was conventional trellis coding with channel precoding (such as the Tomlinson-Harashima precoding). Although multidimensional trellis codes were examined, it was determined that the simple one-dimensional Ungerboeck codes [33] were suitable meeting up to 5 dB of coding gain (ideal asymptotic coding gain) within a latency of 500 m s.

For the one-dimensional Ungerboeck codes [33], thirty-two states were sufficient to achieve a code gain of 4.0 dB. To achieve 5 dB of coding gain would require implementation of a 512 state code; the challenge here is the design of a decoder such that the implementation loss is minimized and the latency requirement is still met. Two proposals were provided for 512-state trellis codes: one from Pairgain in [36] and the other from Adtran in [37]. Both codes were linear codes claiming coding gains about 5 dB. The commonality is that the two proposed codes used rate one-half convolutional codes, where the convolutional coding was performed on one information bit while the other information bits were passed uncoded. The general structure of the trellis is shown in Figure 4.19, where the value of k is 3 (i.e., for every three information bits, there are four coded output bits).

Figure 4.19. HDSL2 trellis encoder structure.

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To address the numerous codes possible, the agreed trellis code structure includes a programmable nonsystematic feed-forward convolutional encoder that codes the least significant bit of the three-bit information symbol [32]. The structure of the programmable convolutional encoder is shown in Figure 4.20. The convolutional code is a nonsystematic rate one-half code, where for each input data bit there are two output bits. The generator polynomials of the two output paths of the convolutional encoder are

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Figure 4.20. Convolutional encoder structure.

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and

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for outputs Y and Y 1 , respectively. The coefficients a , a 1 , , a 20 and b , b 1 , , b 20 are binary coefficients and the operator "+" represents modulo 2 addition. A reference code having a coding gain of approximately 5 dB has coefficients { a 9 , a 8 , , a } = {0101101110} and { b 9 , b 8 , , b } = {1100110001}; the same coefficients are represented in octal as A = 556 and B = 1461, where all of the digits are octal digits. Another code with approximately the same coding gain has coefficients A = 732 and B = 1063.

The entire trellis code in Figure 4.19 is a rate 3/4 code, where the encoder accepts 3 information bits and outputs 4 coded bits. Because the convolutional code that operates on the least significant bit of the input code word is nonsystematic, the trellis code is also nonsystematic. The remaining two information bits are passed to the symbol mapper uncoded. The coefficients of the convolutional encoder, defined by two 20th order polynomials, are provided by the manufacturer's equipment that contains the receiver. During initialization, the coefficients are passed from receiver to encoder. An advantage of this programmable approach is that manufacturers could provide codes that are suitable to the type of decoder that they have implemented (e.g., a Viterbi decoder or sequential decoder). Also note that with this configuration, it is possible that the upstream and downstream channel could have different trellis codes.

The parallel bits at the output of the trellis encode must be mapped in symbols suitable for transmission on the line. The four bits at the trellis-encoder output are mapped into sixteen possible levels. The bit mapping of each of the levels are shown in Figure 4.21.

Figure 4.21. HDSL2 bit-to-symbol mapping.

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The input bits to the trellis encoder are X 1 (m), X 2 (m), and X 3 (m); the output bits are Y 1 (m), Y 2 (m), Y 3 (m), and Y 4 (m). X 1 (m) is the least significant bit of the trellis coder input bits, and Y 1 (m) is the least significant bit of the output symbol. The table in Figure 4.21 shows the mapping of the trellis encoder output bits to the output symbol. The mapping is also shown pictorially in the constellation diagram in the bottom of the figure.

4.2.8 Channel Precoder

The functional block diagram of the channel precoder is shown in Figure 4.22. The receiver computes the feedback filter coefficients { C 1 , C 2 , , C N ) during the training phase in the initialization process and then transfers the coefficients to transmitter during the parameter exchange phase. The input sequence x ( mT s ) is the output of the bit-to-symbol mapping in the trellis encoder. The output of the feedback filter, v ( mT s ), is computed by

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Figure 4.22. HDSL2 channel precoder.

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where T s is the symbol interval, y ( mT s ) is the precoded output sample, m is the sample time index, and N is number of coefficients in the feedback filter. A modulo-16 operator then operates on the difference between the input sample and feedback filter output sample u ( mT s ). Operation of the modulo-16 block is to find an integer d ( mT s ) such that the sum u ( mT s ) + 2 d ( mT s ) falls between the values of “1 and +1. The resulting value of y ( mT s ) is then u ( mT s ) + 2 d ( mT s ).

In the HDSL2, the receiver determines the value of N and the value is passed on to the transmitter at initialization during the parameter exchange phase. The value of N has minimum value of 128 and a maximum of 180 samples; any value in between is valid.

4.2.9 Spectral Shaper

As described earlier, the spectral shape chosen for HDSL2 is that of OPTIS as proposed in [29]. A plot of the downstream mask is shown in Figure 4.23 and that of the upstream spectrum is given in Figure 4.24.


   
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DSL Advances
DSL Advances
ISBN: 0130938106
EAN: 2147483647
Year: 2002
Pages: 154

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