Existing Technologies


Stephen Goodnick

The exponential increase in the density of integrated circuits (ICs) predicted by Moore's Law has been driven primarily by shrinking the dimensions of the individual semiconductor devices comprising these circuits (Figure 15-1). Smaller device dimensions reduce the size of the circuits and therefore lead to a reduction of overall die area (the actual area partitioned on a silicon wafer corresponding to an individual integrated circuit), thus allowing for more transistors on a single die without negatively impacting the cost of manufacturing. However, getting more functions into each circuit generally leads to larger die size, and that requires larger wafers.

Figure 15-1. Growth of the density of microprocessors according to Moore's Law. The vertical axis is numbers of transistors per chip. (Reprinted by permission of the Intel Corporation; copyright Intel Corporation.)


The workhorse of the semiconductor industry over the past three decades has been the metal oxide semiconductor field effect transistor (MOSFET). Its basic structure is comprised of two conducting regions (a source and a drain) separated by an insulating (oxide) gate over a channel that can be turned on or off; this gate is a simple switch and constitutes the basic building block of computer architectures based on two-state logic.

The critical scale is the gate length, which corresponds to the distance between the source and the drain. As this length is reduced, all the corresponding dimensions of the device decrease in size or scale, according to well-defined scaling rules. In addition to reducing the area per transistor on the die, scaling down the gate length reduces the time it takes to move a charge (electrons) from the source to the drain, increasing the switching speed of the transistor and hence the clock speed at which logic circuits operate.

Successive generations of MOS transistor technologies are characterized in terms of this critical dimension, which, for present state-of-the-art commercial production, has already entered the nanometer (nm) scale dimension regime. Figure 15-2 shows scanning electron microscope photographs of Intel's current production transistors at the so-called 65-nm node, and successively shorter-gate-length devices realized in the research laboratory, down to 15nm. Clearly, present-day transistor technology is nanotechnology.

Figure 15-2. Scaling of successive generations of MOSFETs into the nanoscale regime. (Reprinted by permission of the Intel Corporation; copyright Intel Corporation.)


As semiconductor feature sizes shrink into the nanometer-scale regime, device behavior becomes increasingly problematic as new physical phenomena at short dimensions occur and as limitations in material properties are reached. Clearly, as we scale below 15-nm gate length, we eventually approach dimensions for which the channel is only a few silicon (Si) atoms long, at which point (or even much sooner) conventional MOSFET devices cannot scale further, and a saturation of Moore's Law will occur.

In fact, such a limit is already approaching in terms of the necessary silicon dioxide gate oxide thickness separating the gate metal from the channel, which, for 25-nm gate length technology, must be thinner than 1nm, as predicted by the International Technology Roadmap of Semiconductors (ITRS).[1] Basically, this reduction in thickness is required in order to maintain acceptable drive current, and to maintain charge control of the channel, by locating the gate as close to the channel as possible. This is because of the lateral length scale. One nanometer is only a few atomic layers thick, and for such a thin dielectric, leakage currents through the gate degrade performance and increase power dissipation. Industry is addressing this challenge by developing new dielectric materials with high permittivity, so that the effective gate capacitance is increased for a much thicker dielectric, giving better leakage performance.

Another issue leading to a saturation of Moore's Law is manufacturability as dimensions become smaller. As a semiconductor device becomes smaller, its output characteristics are increasingly sensitive to manufacturing and material imperfections. For example, impurity atoms with a valence higher or lower than Si must be introduced into the Si lattice at dilute concentrations to create free charges for carrying current; otherwise, the Si would be insulating. This process is referred to as "doping" the semiconductor, and in ultrasmall devices, the random position of dopant atoms in the device may cause dramatic changes in the current-voltage characteristics from device to device in very small structures. In a large device with many dopant atoms, this effect averages out, but in very small structures, the potential landscape seen by electrons traversing the source to drain varies widely from device to device because of the particular location of the dopant atoms.

Another source of device-to-device output characteristic variance is random variations in linewidths associated with lithography. Again, in very small devices, such process fluctuations may dominate the characteristics of a particular device. This sensitivity of nanoscale devices to process fluctuations means that not only manufacturing but also circuit and architecture design techniques must be developed to anticipate large device-to-device variations and even failures (fault-tolerant design).

To meet the challenges of shrinking gate lengths further into the nanometer-scale regimeincreasing device performance and still maintaining control of charge in the channel with the gateindustry is moving away from the "classic" planar, bulk Si MOSFET design used during the past two decades. To increase performance for a given gate length, there is an increased trend toward alternative materials grown in the active regions of the device, such as strained Si, alloys of Si and Ge, and even compound semiconductors. Such alternatives to bulk Si increase performance through superior transport properties and hence faster switching.

To maintain charge as gate lengths shrink, research and production device structures are becoming increasingly nonclassical and three-dimensional rather than planar. These designs use Si on insulator technology (where a buried layer of oxide is introduced to isolate the device from the Si substrate), dual-gate and wraparound gates (in which the gate is above, below, and around the sides of the channel rather than simply on top), and nanowire shaped channels.

Figure 15-3 illustrates one such technology, the so-called FinFET (due to the fin-shaped gate). The structure is 3-D, and the channel resembles a 1-D wire with nanometer-scale dimensions (nanowire). This wirelike nature of the channel becomes important in the consideration of future technologies based on self-organized 1-D conductors such as carbon nanotubes (CNTs) and self-assembled semiconductor nanowires.

Figure 15-3. Nonclassical device structures. At left is a schematic of a FinFET; at right is an SEM photo of a multileg FinFET structure. (Reprinted by permission of the Intel Corporation; copyright Intel Corporation.)


Beyond these material and manufacturing issues, there are fundamental limits as device dimensions shrink. One is that quantum mechanics starts to play a role at small dimensions, in terms of the wavelike properties of charge carriers such as electrons. Effects such as quantization of motion, interference effects, and tunneling are all physical effects that modify the performance of devices at small dimensions.

Another limit is the discrete nature of charge. In small structures, charge can no longer be treated as a continuous fluid; rather, the number of charges is finite and small, leading to so-called single-electron charging effects. For very small structures, the change in energy and potential (voltage) due to one charge tunneling or otherwise moving from one conductor to another gives rise to a noticeable fluctuation in voltage. This sensitivity is because the capacitance (that is, the proportionality between charge and voltage, D Q = CDV) is a geometrical quantity that reduces as the structure size shrinks. If C is sufficiently small (10-17F and less), then the change in voltage, DV, for a single electron moving from one side to the other (DQ = 1.6 x 10-19C) may be larger than the thermal voltage, 25mV at room temperature.

All these effects can lead to noticeable degradation of the performance of classical and nonclassical MOSFETs, eventually leading to the end of the road map for scaling. Beyond that, there has been extensive work over the past decade related to nanoelectronic or quantum-scale devices, which actually use quantum mechanical and single-electron effects and operate on very different principles from conventional MOSFET devices. These alternatives may allow continued scaling beyond the end of the current scaling road map, as discussed later.

Future Nanoelectronic Device Technologies

As discussed earlier, as semiconductor device dimensions shrink to the nanoscale and beyond, the physics governing device behavior becomes complicated because of several factors. For large-dimension devices, the picture of macroscopic current flow in a device is analogous to fluid flow, in which charges and charge flow (current) appear continuous, and their motion is described by the same classical hydrodynamic equations used in the field of fluid mechanics. As we shrink to small dimensions, itís easy to see that at some level, charge is no longer continuous and that the motion of individual electrons becomes important in the behavior of nanoscale devices.

On the one hand, this sensitivity to individual unwanted charges threatens the reliability and reproducibility of nanoscale CMOS devices. On the other hand, the ability to control the state of individual electrons, and correspondingly to represent and store information, represents the ultimate limit of nanoscale device technology, which is the basis of so-called single-electron transistors and memory discussed later.

Another way in which the electronic behavior of small structures differs from that of macroscale systems is that electrons are governed by the laws of quantum mechanics, where matter exhibits both wavelike and particlelike behavior. One important length scale is the so-called De Broglie wavelength of an electron, which is the characteristic wavelength of matter waves in the quantum mechanics picture. The interaction of electrons with structures on this length scale resembles optics rather than classical dynamics, with effects such as diffraction, interference, quantization of motion, and tunneling, all of which lead to marked changes from the classical fluid picture of charge transport. Such wavelike behavior can persist over long dimensions, depending on the so-called phase coherence length, that is, the length over which an electron "wave" remains coherent.

Quantum computing is a new paradigm that explicitly depends on maintaining phase coherence, and using the potential information stored in the phase of a quantum mechanical two-state system, to exponentially extend the processing power compared with a simple binary logic system based on the same two states. Coherence is destroyed by the interaction of the electron with its energy-dissipative environment, primarily the vibrational motion of the host material in inorganic and organic structures. Because this vibrational motion increases with increasing temperature and thereby reduces the coherence length, quantum mechanical effects tend to wash out at room temperature. At room temperature, phase coherence lengths in Si, for example, are only a few tens of nanometers.

Generally, with regard to the behavior of conventional Si MOSFETs, single-charge and quantum mechanical effects adversely affect performance, creating barriers to further scaling at some future limit that is rapidly being approached, as discussed earlier. Beyond field effect transistors, however, there have been numerous proposals and demonstrations of device functionality and circuits based on single-electron and quantum mechanical effects. These include quantum interference, negative resistance, and single-electron devices, which are realized in metals, semiconductors, nanowires, carbon nanotubes, and molecular systems, as discussed in more detail later.

As dimensions become shorter than the phase-coherence length of electrons, the quantum mechanical wave nature of electrons becomes increasingly apparent, leading to phenomena such as interference, tunneling, and quantization of energy and momentum as discussed earlier. In fact, as was elegantly pointed out by IBM physicist Rolf Landauer, for a one-dimensional conductor such as a nanowire, the system is very analogous to an electromagnetic waveguide with "modes," each supporting a conductance less than or equal to a fundamental constant 2e2/h.

Such quantization of conductance was first demonstrated at Cambridge University and Delft University in the late 1980s, in specially fabricated, split-gate field effect transistors at low temperatures, where the split gate formed a one-dimensional channel in a field effect device. However, manifestations of quantized conductance, such as universal conductance fluctuations, noise, and the quantum Hall effect, appear in many transport phenomena. Many schemes were proposed for quantum interference devices based on analogies to passive microwave structures, such as directional couplers and even coupled waveguides for quantum computing. Promising results have been obtained on ballistic Y-branch structures by the research group in Lund, Sweden, where nonlinear switching behavior and elementary logic functions have been demonstrated, even at room temperature.

Most attempts at realizing quantum coherent devices suffer from the same problems as scaling of conventional nanoscale MOSFETs: the difficulty in controlling the desired waveguide behavior in the presence of unintentional disorder. This disorder can arise from the discrete impurity effects discussed earlier, as well as the difficulty of process control at true nanometerscale dimensions. A further fundamental limit to devices based on the quantum mechanical nature of matter at the nanoscale is the phase coherence length and phase coherence time for maintaining a quantum coherent state. As mentioned earlier, this time and length scale is typically quite short in Si at room temperature.

In recent years, scientists have been attempting to exploit another purely quantum mechanical aspect of charge particles for nanodevice applications: that of electron spin. "Spin" refers to the intrinsic magnetic moment associated with elementary particles such as electrons, an effect that can manifest itself only through measurement relative to some particular reference frame in one of two states: spin-up or spin-down. This twentieth-century discovery has no classical analog, although the name itself implies an origin of magnetic moment due to a charge particle spinning around its own axis to generate a magnetic field.

In terms of the practical manifestation of spin, the ferromagnetic behavior of materials used in, for example, magnetic memory (a multibillion-dollar industry) is intrinsically associated with the interaction of spin states to form an ordered magnetic system. For nanoscale devices, the fact that there are two distinct states associated with spin has attracted researchers to the ability to encode information, either as simply binary information or as a prototypical "qubit" for quantum information storage. One of the main advantages of controlling the quantum state of spin is that spin is much more robust at preserving phase coherence compared with the ordinary quantum mechanical phase of an electron discussed earlier in connection with quantum interference-type devices. Typical spin coherence times in semiconductors can vary from nanoseconds to milliseconds, something that provides much more opportunity to realize quantum coherent devices for applications such as quantum computing.

Previously we mentioned the role of individual random charges as an undesirable element in the reproducibility of nanoscale FETs due to device-to-device variations. However, the discrete rather than continuous nature of charge of individual electrons at the nanolevel, and control of the motion of such electrons, is the basis of a great deal of research in single-electron devices and circuits. The understanding of single-electron behavior is most easily provided in terms of the capacitance, C, of a small tunnel junction (that is, two small conductors separated by a very thin insulator).

As mentioned earlier, capacitance is the proportionality constant relating the voltage difference between a pair of conductors to the net charge (positive on one, negative on the other) on the conductors; the simplest example is a parallel plate capacitor formed by two plates separated by an insulator. If a single electron tunnels across the thin junction from one side to the other, the change in net charge on the conductors results in a corresponding change in electrostatic energy, e2/C. When physical dimensions are sufficiently small, the capacitance (which is primarily a geometrical) is correspondingly small, so that the change in energy may be greater than the thermal energy, 3/2kT, resulting in the possibility of a "Coulomb blockade," or suppression of conductance due to the necessity to overcome this electrostatic voltage barrier. This Coulomb blockade effect allows the experimental control of electrons to tunnel one by one across a junction in response to a separate control gate, which can be used to lower this voltage barrier.

Figure 15-4 illustrates the operation of a so-called single-electron transistor, consisting of two tunnel junctions connecting to a conducting "island" or "quantum dot," to which a second voltage source Vg, is connected through a separate gate capacitor, Cg. As the gate voltage is increased, the Coulomb blockade is lifted when integer numbers of electrons tunnel through the structure, hence allowing control of electron motion one by one. Single-electron transistors, turnstiles, pumps, elementary logic circuits, and single-electron memories have been demonstrated experimentally, functioning even up to room temperature. Room-temperature operation is important for practical applications in that it does not require special cooling or cryogenic technology, which would limit the applicability for, for example, portable electronics. As in the case of quantum interference devices, the technological difficulties arise from fluctuations due to random charges and other sources of manufacturing variation, as well as the difficulty in realizing lithographically defined structures with sufficiently small dimensions to have single-electron charging energies larger than the thermal energy, 25meV@300K.

Figure 15-4. Schematic representation of a single-electron transistor (SET) consisting of two tunnel junctions connecting a conducting island, biased by drain-source voltage and controlled by gate voltage, Vg. During off resonance, electrons see a "gap" in energy, which prevents tunneling. Applying a voltage to the island through the gate allows electrons to tunnel one at a time, giving rise to a peak in conductivity.


There has been rapid progress in realizing functional nanoscale electronic devices based on self-assembled structures such as semiconductor nanowires (NWs) and carbon nanotubes. Semiconductor nanowires have been studied during the past decade in terms of their transport properties, and for nanodevice applications such as resonant tunneling diodes, single-electron transistors, and field effect structures.

Recently, there has been a dramatic increase in interest in NWs because of the demonstration of directed self-assembly of NWs via epitaxial growth. Figure 15-5 shows a scanning electron micrograph of such structures grown using vapor-liquid-solid epitaxy, where the dimensions of the nanowires are less than 10nm. Such semiconductor NWs can be elemental (Si,Ge) or III-V semiconductors, where it has been demonstrated that such wires may be controllably doped during growth, and abrupt compositional changes forming high-quality -D heterojunctions can be achieved. Groups such as those at Harvard and Lund, Sweden, have demonstrated nanowire FETs, bipolar devices, and complementary inverters synthesized using self-assembly. The ability to controllably fabricate heterostructure nanowires has led to demonstration of nanoelectronic devices such as resonant tunneling diodes and single-electron transistors. The scalability of arrays of such nanowires to circuits and architectures has also begun to be addressed, although the primary difficulty is in the inability to grow and orient NWs with desired location and direction.

Figure 15-5. Scanning electron micrograph of self-assembled Si nanowires grown by vapor-liquid-solid epitaxy (after T. Picraux et al.).


Carbon nanotubes are currently the focus of considerable attention because of the many remarkable properties of this new structural state of carbon. Figure 15-6 shows a schematic of a CNT that is composed of carbon atoms arranged in a stable tube configuration. It is a highly stable state of matter, very similar in concept to fullerenes like C60 (buckyballs). The structure can be envisioned as a graphite sheet (where the carbon atoms form hexagonal rings), which is rolled in a tube a few nanometers in diameter, as shown in Figure 15-6a. In rolling the tube and joining itself, the carbon rings forming the graphite structure can align in different offset configurations, characterized by their chirality. Depending on the chirality, CNTs can be metallic, semiconducting, or insulating, all the components required in conventional semiconductor IC technology (interconnects, transistors, and dielectrics). Field effect transistors have been fabricated from CNTs, and basic logic functions demonstrated by researchers at IBM and other research laboratories, as shown in Figure 15-6b. The extreme sensitivity of the conductivity of the nanotube to an attached atom or molecule to the wall or tip of the nanotube, also makes CNTs very attractive as sensors, the subject of considerable current research. The primary challenge faced in the evolution of this technology is the directed growth of CNTs with the desired chirality, and positioning on a semiconductor surface, suitable for large-scale manufacturing.

Figure 15-6. (a) Different states of carbon, including diamond, graphite, C60, and a carbon nanotube (right) (from Richard Smalley's image gallery, http://smalley.rice.edu/smalley.cfm); (b) carbon nanotube inverter formed from p- and n-channel FETs (from IBM, with permission).


Perhaps the ultimate limit of size scaling are devices comprised of a small number of molecules, forming the basis of electronic systems realized with molecular devices, or molecular electronics (moltronics). Figure 15-7 shows a schematic diagram of a nanoscale contact to a molecular device, through which current is passed. Here the molecular device is an organic chain to which different side groups or molecules are attached to realize a desired functionality. The molecular chain structure shown in the lower half of the figure, studied by Mark Reed (Yale) and James Tour (Rice), showed "negative differential conductance (NDC)" in the current voltage characteristics, that is, a decreasing current with increasing voltage. From a circuit standpoint, NDC appears as a negative resistance, which leads to signal amplification and the possibility of bistable behavior because the circuit does not like to reside in the regime, which is the basis for elementary switching devices. Elementary molecular electronic architectures have been demonstrated by HP Research Laboratories using crossbar-type logic.

Figure 15-7. A molecular "junction" (left), and the corresponding molecular device contacted by external leads.


A very attractive feature of molecular systems is the possibility of bottom-up or self-assembly of functional systems. Such templated self-assembly is of course the basis of biological systems, which have exquisite complexity and functionality as well as self-replication and self-repair. Such "biomimetic" approaches to molecular circuits would represent an inexpensive alternative to the exponentially increasing cost of top-down nanofabrication, which is currently driving fab costs into the billions of dollars. However, at present there is no clearcut manufacturing approach to self-assembly in the near term.

Another difficulty in understanding and using molecular electronic structures is the need to separate the intrinsic behavior of a molecular device from the contacts themselves. In conventional devices, contacts are nearly ideal, providing a connection to the other devices and the external world through interconnects, and not affecting the intrinsic performance of devices except through well-controlled parasitic contact resistances. As the number of devices per chip scales exponentially, the number of contacts and interconnects per device increases even faster, and from an architecture standpoint, system performance is increasingly dominated by the interconnects and not the devices themselves. In a nanoscale devices, the contacts may in fact dominate the performance of the device, and at a minimum they are an integral part of the device. This problem is particularly evident in molecular electronic devices, as the schematic of Figure 15-7 indicates (where the contact is much larger than the device). This challenge remains one of the many issues to be solved in evolving molecular electronics in the future.




Nanotechnology. Science, Innovation, and Opportunity
Nanotechnology: Science, Innovation, and Opportunity
ISBN: 0131927566
EAN: 2147483647
Year: 2003
Pages: 204

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