D.2 General Registers and NaT Bits

The Itanium architecture defines 128 general-purpose registers (Gr0 Gr127), which are 64 bits in width and can thus accommodate address pointers and either signed or unsigned integers of that size:

graphics/dfig02.gif

Associated with each general register is a 65th bit, called the NaT bit (not a thing). When a NaT bit is set, the CPU knows that the contents of the associated general register cannot be relied upon.

When data from a marked register are used in subsequent calculations, or if a copy is made of the register's contents, the NaT bit will automatically be set for whichever destination register holds the new invalid result. An invalid condition can be carried along through a sequence of instructions beyond the point where it first occurred and be dealt with whenever convenient. NaT bits are important in software that uses speculative loads.

Table D-1 gives the nomenclature and standardized uses of the Itanium general registers. A register is constant if its value is permanently defined at the hardware level. A register is special if it has some purpose assigned to it, either at the hardware level or by software convention. A register is scratch if it may be freely used by a routine at any calling level (caller must save anything important). A register is preserved if a calling routine depends on its contents (any called procedure must save and restore its contents for its caller). A register is automatic if its name (number) only has a dynamic correspondence to a physical register; such registers are automatically spilled to and filled from memory at allocation times by the hardware, as necessary.

Table D-1. Itanium General Registers

Register

Assembler Name

Other Name

Class

Usage Notes

Gr0

r0

 

Constant

Always 0; writes illegal

Gr1

r1

gp

Special

Global data pointer

Gr2 Gr3

r2 r3

 

Scratch

Useful with addl instruction

Gr4 Gr7

r4 r7

 

Preserved

 

Gr8 Gr11

r8 r11

ret0 ret3

Scratch

Integer values returned by a function

Gr12

r12

sp

Special

Stack pointer (always modulo 16)

Gr13

r13

tp

Special

Thread pointer (if supported by operating system)

Gr14 Gr31

r14 r31

 

Scratch

 

Gr32 Gr39

r32 r39

in0 in7

Automatic

Up to 8 input arguments to a function

Gr32 Gr127

r32 r127

 

Automatic

Stacked input registers; safe

Gr32 Gr127

r32 r127

loc0 loc95

Automatic

Stacked local registers; safe

Gr32 Gr127

r32 r127

out0 out95

Automatic

Stacked output registers

Gr32 Gr127

r32 r127

 

Automatic

Rotating registers in groups of 8; they overlap (overwrite) stacked registers of the current procedure

General registers Gr16 Gr31 exist in duplicate banks, one bank for application code and the other for interrupt handler code in an operating system. Switching register banks can occur much faster than saving some register contents to memory in order to provide working registers for interrupt handlers.



ItaniumR Architecture for Programmers. Understanding 64-Bit Processors and EPIC Principles
ItaniumR Architecture for Programmers. Understanding 64-Bit Processors and EPIC Principles
ISBN: N/A
EAN: N/A
Year: 2003
Pages: 223

flylib.com © 2008-2017.
If you may any questions please contact us: flylib@qtcs.net