53.

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Chapter Review

In this chapter, we have built on top of the simple gate logic introduced in Chapter 2. In particular, we examined the conversion of AND/OR and OR/AND networks into NOR-only and NAND-only logic. Under certain conditions, an additional inverter must be added at the output, so these conversions change two-level logic to a three-level form.

We introduced our first form of complex logic: AND-OR-Invert and OR-AND-Invert gates. Using these building blocks, it is possible to reduce significantly the number of packages needed to implement some functions of moderate levels of complexity.

We examined the concept of multilevel logic and introduced its advantages in terms of reduced literal counts and simplified wiring complexity. Of course, multilevel logic introduces the possibility of in-creased circuit delay by placing additional levels of gates between inputs and outputs. In general, two-level logic yields the fastest implementations and multilevel logic results in circuits with fewer wires.

We described a tool for multilevel logic optimization, misII, and discussed how it can be used to assist in multilevel circuit designs. To use the tool to its best effect, you really must understand the underlying mathematical structure of factored Boolean expressions. However, with standard command scripts supplied with misII, even novice designers can use the tools to create good multilevel designs.

We looked at time response in combinational logic networks and introduced the concept of timing hazards and methods for building hazard-free logic circuits. It should be pointed out that hazards are a problem primarily in circuits without a global clock. We will have more to say about clocked circuits in Chapter 6.

The final section dealt with several important practical matters. These were reading component specifications from a data book; performing simple calculations to determine delays, power consumption, and circuit fan-out; and wiring up switches and LEDs as circuit inputs and outputs.

For a detailed presentation of multilevel logic optimization techniques, the following papers are highly recommended: K. Bartlett, W. Cohen, A. DeGeus, G. Hachtel, "Synthesis and Optimization of Multi-Level Logic under Timing Constraints," IEEE Transactions on Computer-Aided Design, CAD-5, 4, 582-596 (October 1986), and R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, A. R. Wang, "MIS: A Multiple-Level Logic Optimization System," IEEE Transactions on Computer-Aided Design, CAD-6, 6, 1062-1081 (November 1987). The latter is the definitive theoretical treatment of the algorithms at the heart of misII's approach to multilevel logic optimization.

We have based our discussion of hazards on Unit 26 of the classical text by C. H. Roth, Jr., Fundamentals of Logic Design, 3rd Edition, West Publishing Co., St. Paul, MN, 1985. Even he goes lightly over the discussion of dynamic hazards. A more detailed discussion of this topic can be found in E. J. McCluskey's earlier textbook, Introduction to the Theory of Switching Circuits, McGraw-Hill, New York, 1965.

All manufacturers provide data books for their components. The standard reference for TTL components can be obtained from Texas Instruments, the manufacturer that has most popularized the 74XX series. The most critical volumes of their five-volume set are Volume 2, which describes standard, S, and LS TTL, and Volume 3, which describes ALS and AS components.

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This file last updated on 07/07/96 at 18:44:30.
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What is Sarbanes-Oxley[q]
What is Sarbanes-Oxley[q]
ISBN: 71437967
EAN: N/A
Year: 2006
Pages: 101

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